----------------------------------------------------------------------------------
-- Company: 			LBNL
-- Engineer: 			Dionisio Doering
-- 
-- Create Date:    	18:11:46 12/07/2006 
-- Design Name: 		Optical interface CPLD
-- Module Name:    	NIDAQLogic - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices: 	XC95288TQ144-7
-- Tool versions: 	ISE 8.2
-- Description: 		
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity NIDAQLogic is
    Port ( 
				rst 				: in  STD_LOGIC;
				clk 				: in  STD_LOGIC;
				-- National Instruments board signals
				DIOA 				: in  STD_LOGIC_VECTOR (7 downto 0);
				DIOB 				: in  STD_LOGIC_VECTOR (7 downto 0);
				DIOC 				: out STD_LOGIC_VECTOR (7 downto 0);
				DIOD 				: out STD_LOGIC_VECTOR (7 downto 0);
--				PCLK1 			: in  STD_LOGIC;
				STOPTRIG1	 	: out STD_LOGIC;
				REQ1 				: out STD_LOGIC;
				ACK1 				: in  STD_LOGIC;
--				PCLK2 			: in  STD_LOGIC;
				STOPTRIG2 		: out STD_LOGIC;
				REQ2 				: out STD_LOGIC;
				ACK2 				: in  STD_LOGIC;
				-- FIFO interface
				FIFO_Q 			: in  STD_LOGIC_VECTOR (15 downto 0);
				EFn 				: in  STD_LOGIC;
				RCLK	 			: out STD_LOGIC;
				RENn 				: out STD_LOGIC;
				OEn 				: out STD_LOGIC;
				-- Main Logic
				NICMD_Ready		: out STD_LOGIC;							--Goes high when a new command is present
				NICMD				: out STD_LOGIC_VECTOR (7 downto 0);--command
				NICMD_Arg		: out STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				NICMD_Ack		: in  STD_LOGIC;							--command ack
				StatusData		: in  STD_LOGIC_VECTOR (15 downto 0);--Data that will be sent to PC (status)
				SendDataCmd		: in  STD_LOGIC;							--Command that tell this module to send the data
				NILogicBusy		: out STD_LOGIC;							--this module is busy
				EventReadout	: in  STD_LOGIC;							--Event was readout
				DataPackageSize: in  STD_LOGIC_VECTOR (15 downto 0);--size of the data package, typically 4096 words				
				NIStatus			: out STD_LOGIC_VECTOR ( 7 downto 0)
			  );
end NIDAQLogic;

architecture Behavioral of NIDAQLogic is
---------------------------------------------------
-- Component Declaration								 --
---------------------------------------------------
component NI_Interface is
	Port ( 
				rst 			: in  STD_LOGIC;
				clk 			: in  STD_LOGIC;
				ACK1			: in  STD_LOGIC;
				ACK2 			: in  STD_LOGIC;
				REQ1 			: out STD_LOGIC;
				REQ2 			: out STD_LOGIC;
				data_in 		: in  STD_LOGIC_VECTOR(15 downto 0);
				wen 			: in	STD_LOGIC;
				wdone 		: out	STD_LOGIC;
				command_out	: out	STD_LOGIC_VECTOR(15 downto 0);
				cav 			: out STD_LOGIC;								-- Command AVailable
				PORT1 		: in  STD_LOGIC_VECTOR(15 downto 0);
				PORT2 		: out STD_LOGIC_VECTOR(15 downto 0)
			);
end component;

type NIDAQSTATE_TYPE is (IDLE, CMDRECEIVEDST, READFIFOST, WAITSENDPACKAGEST, SENDPACKAGEST, SENDDATAST, WAITWRITEST);

---------------------------------------------------
-- Signal Declaration									 --
---------------------------------------------------
--internal signals
signal NIDAQSTATE					: NIDAQSTATE_TYPE;
signal SendingPackageFlag 		: std_logic;
signal NumOfWordsSentCounter	: std_logic_vector(7 downto 0);
signal Readtimeoutcounter		: std_logic_vector(15 downto 0);--(27 downto 0);
signal Readtimeouten				: std_logic;
signal Readtimeout				: std_logic;
-- Signals for National Instruments interface controller
signal PORT1 						: std_logic_vector(15 downto 0);
signal PORT2 						: std_logic_vector(15 downto 0);
signal NIdata_in 					: STD_LOGIC_VECTOR(15 downto 0);
signal command_out			 	: std_logic_vector(15 downto 0);
--signal dreq 						: std_logic;
signal cav				 			: std_logic;
signal cav1sig, cav2sig			: std_logic;
signal wen 							: std_logic;
signal wdone 						: std_logic;

-- Main Logic Signals
signal StatusDatasig				: std_logic_vector(15 downto 0);
signal NICMDsig					: std_logic_vector( 7 downto 0);
signal NICMD_Argsig				: std_logic_vector( 7 downto 0);

begin
---------------------------------------------------
-- Signal Connections									 --
---------------------------------------------------

--StatusDatasig	<= StatusData;
NICMD			<= NICMDsig;
NICMD_Arg	<= NICMD_Argsig;

--FIFO signals
--the output of the FIFO is enabled while sending data
OEn <= '0';--SendingPackageFlag;
RCLK <= clk;

-- Build the 16-bit ports from the 8-bit ports
-- Data from National Instruments DIO board
PORT1(7 downto 0)		<=DIOB;
PORT1(15 downto 8)	<=DIOA;
-- Data to DIO board
DIOC						<=PORT2(7 downto 0);
DIOD						<=PORT2(15 downto 8);
--this stop signals are not used so they are set all the time
STOPTRIG1 <= '1';
STOPTRIG2 <= '1';

--Read time out process,
--this avoids the firmware to be locked by waiting a read forever.
Readtimeoutproc : process (clk, rst, Readtimeouten, Readtimeoutcounter)
begin
	if(rst = '1') then
		Readtimeoutcounter <= (others => '0');
		Readtimeout <= '0';
	elsif (clk'event and clk = '1') then
		if (Readtimeouten  = '1') then
			Readtimeoutcounter <= Readtimeoutcounter + 1;
			--change the flag state
			if (Readtimeoutcounter = x"F080") then --x"0FAF080") then -- O.5 seconds
				Readtimeout <= '1';
			else
				Readtimeout <= '0';
			end if;
		else
			Readtimeoutcounter <= (others => '0');
			Readtimeout <= '0';
		end if;
	end if;
end process;

--Process that implements the SendingPackageFlag
SendingPackageFlagproc : process (clk, rst, EventReadout, DataPackageSize, NumOfWordsSentCounter)
begin
	if(rst = '1') then
		NumOfWordsSentCounter 		<= x"10";--DataPackageSize+1;
		SendingPackageFlag 	<= '0';
	elsif (clk'event and clk = '1') then
		if (SendingPackageFlag = '1') then-- implements a down couter
			if(wen = '1') then
				NumOfWordsSentCounter <= NumOfWordsSentCounter - 1;
			else
				NumOfWordsSentCounter <= NumOfWordsSentCounter;
			end if;
		else
			NumOfWordsSentCounter 		<= x"10";--DataPackageSize+1;
		end if;
		--implements the flag behavior, where the flag is set by a readout command
		--and reseted when the number of data sent is iqual to the data package size.
		if (EventReadout = '1' and EFn = '1') then
			SendingPackageFlag <= '1';
		elsif (NumOfWordsSentCounter = x"00") then
			SendingPackageFlag <= '0';
		else
			SendingPackageFlag <= SendingPackageFlag;
		end if;
	end if;
end process; 

--NIDAQ State machine
NIDAQSMproc : process (clk, rst, NIDAQSTATE)
begin
	if (rst = '1') then
		RENn 			<= '1';--FIFO
		wen			<= '0';--DIO
		NIdata_in	<= (others => '0');	
		NICMD_Ready	<= '0';
		NICMDsig		<= (others => '0');	
		NICMD_Argsig<= (others => '0');
		NILogicBusy	<= '0';
		NIStatus		<= (others => '0');
		Readtimeouten <= '0';
		-- next state logic
		NIDAQSTATE <= IDLE;
	elsif (clk'event and clk = '1') then
		StatusDatasig <= StatusData;--latch the status data
		cav1sig <= cav;
		cav2sig <= cav1sig;
		NIStatus(3) <= cav;
		case (NIDAQSTATE) is
			when CMDRECEIVEDST =>
				RENn 			<= '1';
				NICMD_Ready	<= '1';
				NICMDsig		<= command_out(15 downto 8);--x"65";--command_out(15 downto 8);	
				NICMD_Argsig<= command_out( 7 downto 0);
				wen			<= '0';--DIO
				NIdata_in	<= NIdata_in;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "001";
				Readtimeouten <= '0';
				-- next state logic
				NIDAQSTATE <= IDLE;
			when READFIFOST =>
				RENn 			<= '0';--FIFO
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '0';--DIO
				NIdata_in	<= NIdata_in;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "010";
				Readtimeouten <= '0';
				-- next state logic
				NIDAQSTATE <= WAITSENDPACKAGEST;
			when WAITSENDPACKAGEST =>
				RENn 			<= '1';
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '0';--DIO
				NIdata_in	<= FIFO_Q;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "011";
				Readtimeouten <= '0';
				-- next state logic
				NIDAQSTATE <= SENDPACKAGEST;
			when SENDPACKAGEST =>
				RENn 			<= '1';
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '1';--DIO
				NIdata_in	<= FIFO_Q;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "111";
				Readtimeouten <= '0';
				-- next state logic
				NIDAQSTATE <= WAITWRITEST;
			when SENDDATAST =>
				RENn 			<= '1';
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '1';--DIO
				NIdata_in	<= StatusDatasig;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "100";
				Readtimeouten <= '0';
				-- next state logic
				NIDAQSTATE <= WAITWRITEST;
			when WAITWRITEST =>
				RENn 			<= '1';
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '0';--DIO
				NIdata_in	<= NIdata_in;
				NILogicBusy	<= '1';	
				NIStatus(2 downto 0) <= "101";
				Readtimeouten <= '1';
				-- next state logic
				if (wdone = '1' or Readtimeout = '1') then
					NIDAQSTATE <= IDLE;
				else
					NIDAQSTATE <= NIDAQSTATE;
				end if;
			when others => --IDLE
				RENn 			<= '1';
				NICMD_Ready	<= '0';
				NICMDsig		<= NICMDsig;	
				NICMD_Argsig<= NICMD_Argsig;
				wen			<= '0';--DIO
				NIdata_in	<= NIdata_in;
				NILogicBusy	<= '0';	
				NIStatus(2 downto 0) <= "110";
				Readtimeouten <= '0';
				-- next state logic
				if (cav = '1') then --if (cav2sig = '1') then 
					NIDAQSTATE <= CMDRECEIVEDST;
				elsif (SendingPackageFlag = '1') then
					NIDAQSTATE <= READFIFOST;
				elsif (SendDataCmd = '1') then
					NIDAQSTATE <= SENDDATAST;
				else
					NIDAQSTATE <= NIDAQSTATE;
				end if;
		end case;
	end if;
end process;

-- Controller for National Instruments board
NI_Interfacecomp : NI_Interface 
	PORT MAP(
					rst 			=> rst,				-- main reset (active high)
					clk 			=> clk,				-- main clock (40MHz)
					ACK1 			=> ACK1,				-- DIO ready port 1 (active low, from DIO)
					ACK2 			=> ACK2,				-- DIO ready port 2 (active low, from DIO)
					data_in 		=> NIdata_in,		-- data to send to DIO
					wen			=> wen,				-- initiate write to DIO
					wdone 		=> wdone,			-- indicate end of write cycle
					REQ1 			=> REQ1,				-- DAQ ready port 1 (active low, to DIO)
					REQ2 			=> REQ2,				-- DAQ ready port 2 (active low, to DIO)
					command_out => command_out,	-- commands sent by the DIO
					cav 			=> cav,				-- indicates command is available
					PORT1 		=> PORT1,			-- port 1 (data to DIO)
					PORT2 		=> PORT2				-- port 2 (data from DIO = commands)
				);
	
end Behavioral;