----------------------------------------------------------------------------------
-- Company: 			LBNL
-- Engineer: 			Dionisio Doering
-- 
-- Create Date:    	18:04:24 12/07/2006 
-- Design Name: 		Optical interface CPLD
-- Module Name:    	MainLogic - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices: 	XC95288TQ144-7 
-- Tool versions: 	ISE 8.2
-- Description: 		This module implements the main state machine for the interface
--							board.
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MainLogic is
    Port (	rst 					: in  STD_LOGIC;
				clk 					: in  STD_LOGIC;
				-- FIFO interface
				FFn 					: in  STD_LOGIC;
				HFn 					: in  STD_LOGIC;
				EFn 					: in  STD_LOGIC;
				RSTn 					: out STD_LOGIC;
				--NIDAQ Logic
				NICMD_Ready			: in  STD_LOGIC;							--Goes high when a new command is present
				NICMD					: in  STD_LOGIC_VECTOR (7 downto 0);--command
				NICMD_Arg			: in  STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				NICMD_Ack			: out STD_LOGIC;							--command ack
				NILogicBusy			: in  STD_LOGIC;							--this module is busy				
				StatusData			: out STD_LOGIC_VECTOR (15 downto 0);--Data that will be sent to PC (status)
				SendDataCmd			: out STD_LOGIC;							--Command that tell this module to send the data
				-- GLINK interface
				D 						: in  STD_LOGIC_VECTOR (15 downto 0);
				DATAOK 				: in  STD_LOGIC;
				RXREADY 				: in  STD_LOGIC;
				RXDATA 				: in  STD_LOGIC;
				RXERROR 				: in  STD_LOGIC;
			  --Optical Logic
				OPTCMD_Ready		: out STD_LOGIC;							--Goes high when a new command is present
				OPTCMD				: out STD_LOGIC_VECTOR (7 downto 0);--command
				OPTCMD_Arg			: out STD_LOGIC_VECTOR (7 downto 0);--command argument (if needed)
				OPTCMD_Ack			: in  STD_LOGIC;							--command ack
				OPTLogicBusy		: in  STD_LOGIC;							--this module is busy
				--RXDatasig
				EventReady			: in  STD_LOGIC;							--One full event is stored in the FIFO
				--Main Logic output
				EventReadout		: out STD_LOGIC;							--Event was readout
				DataPackageSize	: out STD_LOGIC_VECTOR (15 downto 0) --size of the data package, typically 4096 words
			 );
end MainLogic;

architecture Behavioral of MainLogic is

type MAINSTATE_TYPE is (IDLE, READOUTCMDST, SIMULDATACMDST, HWSTATUSST, GLINKDATAST, SENDCOMMANDST);

---------------------------------------------------
-- Signal Declaration									 --
---------------------------------------------------
--internal signals
signal MAINSTATE		: MAINSTATE_TYPE;
--signal HWStatusReg	: STD_LOGIC_VECTOR (15 downto 0); -- latched version of the status
signal HWStatusRegsig: STD_LOGIC_VECTOR (15 downto 0); -- connects to all signal
signal StatusDatasig	: STD_LOGIC_VECTOR (15 downto 0);
signal OPTCMDsig		: STD_LOGIC_VECTOR ( 7 downto 0);
signal OPTCMD_Argsig	: STD_LOGIC_VECTOR ( 7 downto 0);

begin

---------------------------------------------------
-- Signal Connections									 --
---------------------------------------------------

--Hardware status signal connection
HWStatusRegsig(0) <= not EFn;
HWStatusRegsig(1) <= not FFn;
HWStatusRegsig(2) <= not HFn;
HWStatusRegsig(3) <= DATAOK;
HWStatusRegsig(4) <= RXREADY;
HWStatusRegsig(5) <= RXDATA;
HWStatusRegsig(6) <= RXERROR;
HWStatusRegsig(7) <= EventReady;
HWStatusRegsig(15 downto 8) <= (others => '0');

--Hardwire the package size, later this could be a register so the pc could configure it.
DataPackageSize 	<= x"1000";--16 1000 == 4096 decimal
StatusData 			<= StatusDatasig;
OPTCMD				<= OPTCMDsig;			
OPTCMD_Arg	 		<= OPTCMD_Argsig;

--MAIN State machine
MAINSMproc : process (clk, rst, MAINSTATE)
begin
	if(rst = '1') then
		--HWStatusReg 	<= (others => '0');
		RSTn 				<= '0';--FIFO reset
		NICMD_Ack 		<= '0';
		StatusDatasig 	<= (others => '0');
		SendDataCmd		<= '0';
		OPTCMD_Ready	<= '0';
		OPTCMDsig		<= (others => '0');	
		OPTCMD_Argsig	<= (others => '0');
		EventReadout	<= '0';
		-- next state logic
		MAINSTATE <= IDLE;
	elsif (clk'event and clk = '1') then
		case (MAINSTATE) is
			when READOUTCMDST =>
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '1';
				StatusDatasig 	<= StatusDatasig;
				SendDataCmd		<= '0';
				OPTCMD_Ready	<= '0';
				OPTCMDsig		<= OPTCMDsig;	
				OPTCMD_Argsig	<= OPTCMD_Argsig;
				EventReadout	<= '1';
				-- next state logic
				MAINSTATE <= IDLE;
			when SIMULDATACMDST =>
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '1';
				StatusDatasig 	<= StatusDatasig;
				SendDataCmd		<= '0';
				OPTCMD_Ready	<= '1';
				OPTCMDsig		<= x"66";--102dec	
				OPTCMD_Argsig	<= x"00";
				EventReadout	<= '0';
				-- next state logic
				MAINSTATE <= IDLE;
			when SENDCOMMANDST =>
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '1';
				StatusDatasig 	<= StatusDatasig;
				SendDataCmd		<= '0';
				OPTCMD_Ready	<= '1';
				OPTCMDsig		<= NICMD;	
				OPTCMD_Argsig	<= NICMD_ARG;
				EventReadout	<= '0';
				-- next state logic
				MAINSTATE <= IDLE;
			when HWSTATUSST =>
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '1';
				StatusDatasig 	<= HWStatusRegsig;
				SendDataCmd		<= '1';
				OPTCMD_Ready	<= '0';
				OPTCMDsig		<= OPTCMDsig;	
				OPTCMD_Argsig	<= OPTCMD_Argsig;
				EventReadout	<= '0';
				-- next state logic
				MAINSTATE <= IDLE;
			when GLINKDATAST =>
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '1';
				StatusDatasig 	<= D; --GLink data
				SendDataCmd		<= '1';
				OPTCMD_Ready	<= '0';
				OPTCMDsig		<= OPTCMDsig;	
				OPTCMD_Argsig	<= OPTCMD_Argsig;
				EventReadout	<= '0';
				-- next state logic
				MAINSTATE <= IDLE;
			when others => --IDLE
				--HWStatusReg 	<= HWStatusReg;
				RSTn 				<= '1';--FIFO reset
				NICMD_Ack 		<= '0';
				StatusDatasig 	<= StatusDatasig;
				SendDataCmd		<= '0';
				OPTCMD_Ready	<= '0';
				OPTCMDsig		<= OPTCMDsig;	
				OPTCMD_Argsig	<= OPTCMD_Argsig;
				EventReadout	<= '0';
				-- next state logic
				if (NICMD_Ready = '1' and (NICMD(7 downto 5) = "000" or NICMD = x"67")) then
					MAINSTATE <= SENDCOMMANDST;
				elsif (NICMD_Ready = '1' and NICMD = x"64") then
					MAINSTATE <= READOUTCMDST;
				elsif (NICMD_Ready = '1' and NICMD = x"65") then
					MAINSTATE <= HWSTATUSST;
				elsif (NICMD_Ready = '1' and NICMD = x"66") then
					MAINSTATE <= SIMULDATACMDST;
				elsif (NICMD_Ready = '1' and NICMD = x"68") then
					MAINSTATE <= GLINKDATAST;
				else
					MAINSTATE <= MAINSTATE;
				end if;
		end case;
	end if;
end process;

end Behavioral;