----------------------------------------------------------------------------------
-- Company: 			LBNL
-- Engineer: 			Dionisio Doering
-- 
-- Create Date:    	09:24:19 12/06/2006 
-- Design Name: 		Optical interface CPLD
-- Module Name:    	RxDataLogic - Behavioral 
-- Project Name: 		SAO - Multiple Waveform Digitizer System
-- Target Devices: 	XC95288TQ144-7 
-- Tool versions: 	ISE 8.2
-- Description: 		
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RxDataLogic is
    Port ( 
				rst 					: in  STD_LOGIC; --reset
				clk 					: in  STD_LOGIC; --clock
				-- GLINK interface
				D 						: in  STD_LOGIC_VECTOR (15 downto 0);
				DATAOK 				: in  STD_LOGIC;
				RXREADY 				: in  STD_LOGIC;
				RXDATA 				: in  STD_LOGIC;
				RXERROR 				: in  STD_LOGIC;
				-- FIFO interface
				FIFO_D 				: out STD_LOGIC_VECTOR (15 downto 0);
				FFn 					: in  STD_LOGIC;
				HFn 					: in  STD_LOGIC;
				EFn 					: in  STD_LOGIC;
				WCLK 					: out STD_LOGIC;
				WENn 					: out STD_LOGIC;				
				-- Control Logic Interface
				GenSimData			: in  STD_LOGIC;--tell the module to generate the simulated data, simdata has always 4096words
				Busy 					: out STD_LOGIC;--module is busy
				EventReady			: out STD_LOGIC;--One full event is stored in the FIFO
				EventReadout		: in  STD_LOGIC;--Event was readout
				DataPackageSize 	: in  STD_LOGIC_VECTOR (15 downto 0); --size of the data package, typically 4096 words
				ErrorFlag			: out STD_LOGIC--if some error happend, like FIFO is FULL and trying to write more data
			 );
end RxDataLogic;

architecture Behavioral of RxDataLogic is

type RXDATALOGICSTATE_TYPE is (IDLE, GENDATACMDST, GENDATAST,DATARECEIVEDST,WRITEFIFOST);
---------------------------------------------------
-- Signal Declaration									 --
---------------------------------------------------
signal RXDATALOGICSTATE : RXDATALOGICSTATE_TYPE; --state machine states
signal GenDatasig 		: STD_LOGIC; -- Tells the Simulated Data Generator to start working
signal GenDataDonesig 	: STD_LOGIC; -- Flags when the data was completed generated
signal SimulData			: STD_LOGIC_VECTOR(15 downto 0); -- contains the simulated data
signal GenDataCounter	: STD_LOGIC_VECTOR(15 downto 0); -- couter needed to generate the simulated data
signal EventReadyFlag 	: STD_LOGIC; -- Flags when a full event is stored in the FIFO
signal EventReadyCmd		: STD_LOGIC; -- command that sets the EventReadyFlag
signal GLinkDatasig		: STD_LOGIC_VECTOR(15 downto 0); -- Latch to Data received form GLINK
signal EventDataCounter	: STD_LOGIC_VECTOR(15 downto 0); -- Counts the number of data received so far
begin
---------------------------------------------------
-- Signal Connections									 --
---------------------------------------------------
EventReady 	<= EventReadyFlag;
WCLK 			<= clk;
--WENn			<= '0';
--temporary assign
ErrorFlag 			<= '0';

EventDataCounter 	<= (others => '0');

--assyncronous mux for FIFO data
--with RXDATALOGICSTATE select
--FIFO_D 	<=	SimulData when GENDATACMDST,
--				SimulData when GENDATAST,
--				GLinkDatasig when others;
FIFO_D 	<=	SimulData when ((RXDATALOGICSTATE = GENDATACMDST)or(RXDATALOGICSTATE = GENDATAST)) else
				GLinkDatasig;
				
--Event Ready Flag tells when a full event is stored in the FIFO
--This Flag stays set until the system is reseted or the event is readout
EventReadyFlagproc : process (rst, clk, EventReadyCmd, EventReadout)
begin
	if(rst = '1' or EventReadout = '1') then
		EventReadyFlag <= '0';
	elsif (clk'event and clk = '1') then
		if (EventReadyCmd = '1') then
			EventReadyFlag <= '1';
		else
			EventReadyFlag <= EventReadyFlag;
		end if;
	end if;
end process;

--state machine process
--this machines coordinates the simulated data generation
--as well as receinving data from the optical board
RXDATALOGICSMproc :  process (rst, clk, RXDATALOGICSTATE)
begin
	if (rst = '1') then
		GenDatasig 			<= '0';
		Busy 					<= '0';
		EventReadyCmd		<= '0';
		WENn					<=	'1';
		GLinkDatasig 		<= (others => '0');
		RXDATALOGICSTATE 	<= IDLE;
	elsif (clk'event and clk = '1') then
		GLinkDatasig 		<= D; -- Latch GLINK data
		case (RXDATALOGICSTATE) is 
			when GENDATACMDST =>-- starts generating simulated data
				GenDatasig 			<= '1';
				Busy 					<= '1';
				EventReadyCmd		<= '0';
				WENn					<=	'1';
				--if (GenDatasig = '1') then
					RXDATALOGICSTATE 	<= GENDATAST;
				--else
				--	RXDATALOGICSTATE 	<= RXDATALOGICSTATE;
				--end if;
			when GENDATAST => --stays here until all simulated data is generated
				GenDatasig 			<= '1';
				Busy 					<= '1';
				if (GenDataDonesig = '1') then
					WENn					<=	'1'; -- enable data to written into the fifo
					EventReadyCmd		<= '1';
					RXDATALOGICSTATE 	<= IDLE;
				else
					WENn					<=	'0'; -- enable data to written into the fifo
					EventReadyCmd		<= '0';
					RXDATALOGICSTATE 	<= RXDATALOGICSTATE;
				end if;
			when DATARECEIVEDST => --latch received data
				Busy 					<= '1';
				GenDatasig 			<= '0';
				EventReadyCmd		<= '0';
				WENn					<=	'1';
				RXDATALOGICSTATE 	<= WRITEFIFOST;
			when WRITEFIFOST =>	-- writes the received data into the fifo
				GenDatasig 			<= '1';
				Busy 					<= '1';
				if (GenDataDonesig = '1') then
					WENn					<=	'1'; -- enable data to written into the fifo
					EventReadyCmd		<= '1';
					RXDATALOGICSTATE 	<= IDLE;
				else
					WENn					<=	'0'; -- enable data to written into the fifo
					EventReadyCmd		<= '0';
					RXDATALOGICSTATE 	<= RXDATALOGICSTATE;
				end if;
				--GenDatasig 			<= '0';
				--Busy 					<= '1';
				--WENn					<=	'1';
				--if (EventDataCounter = DataPackageSize) then -- issue a command when a full data package is ready
				--	EventReadyCmd		<= '1';
				--else
				--	EventReadyCmd		<= '0';
				--end if;
				--RXDATALOGICSTATE 	<= IDLE;
			when others => --IDLE
				GenDatasig 			<= '0';
				Busy 					<= '0';
				EventReadyCmd		<= '0';
				WENn					<=	'1';
				if (GenSimData = '1') then
					RXDATALOGICSTATE <= GENDATACMDST;
				elsif	(GLinkDatasig = x"AAAA" and DATAOK = '1' and RXERROR = '0')then  --should be 15 but I'm using 0 temporarilly
					--WENn					<=	'0';--if this is enable it writes AAAA into the readout FIFO
					RXDATALOGICSTATE <= WRITEFIFOST;
				else
					RXDATALOGICSTATE <= RXDATALOGICSTATE;
				end if;
		end case;
	end if;
end process;

--process that generate simulated data
IB_SimulDataGen : process (rst, clk, GenDatasig)
begin
	if (rst = '1') then
		GenDataCounter <= (others => '0');
		SimulData		<= (others => '0');
		GenDataDonesig <= '0';
	elsif (clk'event and clk = '1') then
		-- implements the counter
		if (GenDatasig = '0') then
			GenDataCounter <= (others => '0');
		else
			GenDataCounter <= GenDataCounter + 1;
		end if;
		--implement the data generator
--		case (GenDataCounter) is 
--			when x"0000" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"000A";
--			when x"0001" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0009";
--			when x"0002" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0008";
--			when x"0003" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0007";
--			when x"0004" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0006";
--			when x"0005" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0005";
--			when x"0006" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0004";
--			when x"0007" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0003";
--			when x"0008" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0002";
--			when x"0009" =>
--				--GenDataDonesig <= '0';
--				SimulData		<= x"0001";
--			--when x"000F" =>--4095
--				--last word of the simulated data package
--				--GenDataDonesig <= '1';
--				--SimulData		<= GenDataCounter;
--			when others =>
--				--GenDataDonesig <= '0';
--				SimulData		<= GenDataCounter;
--		end case;
--		SimulData		<= GenDataCounter;
		--end condition
		if (GenDataCounter = DataPackageSize-0) then
			GenDataDonesig <= '1';
		else
			GenDataDonesig <= '0';
		end if;
	end if;
end process;

end Behavioral;