-- C:\JFB\XILINX\MWD\WORK\EBEAM\EBEAM
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Mon Mar 08 08:35:41 2004
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY timelatch_tbw IS
END timelatch_tbw;

ARCHITECTURE testbench_arch OF timelatch_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT timelatch
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			msb_in : In  std_logic_vector (14 DOWNTO 0);
			lsb_in : In  std_logic_vector (14 DOWNTO 0);
			msb_out : Out  std_logic_vector (14 DOWNTO 0);
			lsb_out : Out  std_logic_vector (14 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL msb_in : std_logic_vector (14 DOWNTO 0);
	SIGNAL lsb_in : std_logic_vector (14 DOWNTO 0);
	SIGNAL msb_out : std_logic_vector (14 DOWNTO 0);
	SIGNAL lsb_out : std_logic_vector (14 DOWNTO 0);

BEGIN
	UUT : timelatch
	PORT MAP (
		reset => reset,
		clk => clk,
		msb_in => msb_in,
		lsb_in => lsb_in,
		msb_out => msb_out,
		lsb_out => lsb_out
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		clk <= transport '1';
		WAIT FOR 6 ns;
		WAIT FOR 144 ns;
		clk <= transport '0';
		WAIT FOR 144 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_msb_out(
			next_msb_out : std_logic_vector (14 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (msb_out /= next_msb_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns msb_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, msb_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_msb_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_lsb_out(
			next_lsb_out : std_logic_vector (14 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (lsb_out /= next_lsb_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns lsb_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lsb_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_lsb_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		reset <= transport '0';
		msb_in <= transport std_logic_vector'("000000000000000"); --0
		lsb_in <= transport std_logic_vector'("000000000000000"); --0
		-- --------------------
		WAIT FOR 12 ns; -- Time=12 ns
		CHECK_msb_out("000000000000000",12); --0
		CHECK_lsb_out("000000000000000",12); --0
		-- --------------------
		WAIT FOR 138 ns; -- Time=150 ns
		lsb_in <= transport std_logic_vector'("000000000000001"); --1
		-- --------------------
		WAIT FOR 150 ns; -- Time=300 ns
		reset <= transport '1';
		lsb_in <= transport std_logic_vector'("000000000000010"); --2
		-- --------------------
		WAIT FOR 12 ns; -- Time=312 ns
		CHECK_msb_out("000000000000000",312); --0
		CHECK_lsb_out("000000000000010",312); --2
		-- --------------------
		WAIT FOR 138 ns; -- Time=450 ns
		lsb_in <= transport std_logic_vector'("000000000000011"); --3
		-- --------------------
		WAIT FOR 150 ns; -- Time=600 ns
		lsb_in <= transport std_logic_vector'("000000000000100"); --4
		-- --------------------
		WAIT FOR 12 ns; -- Time=612 ns
		CHECK_msb_out("000000000000000",612); --0
		CHECK_lsb_out("000000000000100",612); --4
		-- --------------------
		WAIT FOR 138 ns; -- Time=750 ns
		lsb_in <= transport std_logic_vector'("000000000000101"); --5
		-- --------------------
		WAIT FOR 150 ns; -- Time=900 ns
		lsb_in <= transport std_logic_vector'("000000000000110"); --6
		-- --------------------
		WAIT FOR 12 ns; -- Time=912 ns
		CHECK_msb_out("000000000000000",912); --0
		CHECK_lsb_out("000000000000110",912); --6
		-- --------------------
		WAIT FOR 138 ns; -- Time=1050 ns
		lsb_in <= transport std_logic_vector'("000000000000111"); --7
		-- --------------------
		WAIT FOR 150 ns; -- Time=1200 ns
		lsb_in <= transport std_logic_vector'("000000000001000"); --8
		-- --------------------
		WAIT FOR 12 ns; -- Time=1212 ns
		CHECK_msb_out("000000000000000",1212); --0
		CHECK_lsb_out("000000000001000",1212); --8
		-- --------------------
		WAIT FOR 138 ns; -- Time=1350 ns
		lsb_in <= transport std_logic_vector'("000000000001001"); --9
		-- --------------------
		WAIT FOR 150 ns; -- Time=1500 ns
		lsb_in <= transport std_logic_vector'("000000000001010"); --A
		-- --------------------
		WAIT FOR 12 ns; -- Time=1512 ns
		CHECK_msb_out("000000000000000",1512); --0
		CHECK_lsb_out("000000000001010",1512); --A
		-- --------------------
		WAIT FOR 138 ns; -- Time=1650 ns
		lsb_in <= transport std_logic_vector'("000000000001011"); --B
		-- --------------------
		WAIT FOR 150 ns; -- Time=1800 ns
		lsb_in <= transport std_logic_vector'("000000000001100"); --C
		-- --------------------
		WAIT FOR 12 ns; -- Time=1812 ns
		CHECK_msb_out("000000000000000",1812); --0
		CHECK_lsb_out("000000000001100",1812); --C
		-- --------------------
		WAIT FOR 138 ns; -- Time=1950 ns
		lsb_in <= transport std_logic_vector'("000000000001101"); --D
		-- --------------------
		WAIT FOR 150 ns; -- Time=2100 ns
		lsb_in <= transport std_logic_vector'("000000000001110"); --E
		-- --------------------
		WAIT FOR 12 ns; -- Time=2112 ns
		CHECK_msb_out("000000000000000",2112); --0
		CHECK_lsb_out("000000000001110",2112); --E
		-- --------------------
		WAIT FOR 138 ns; -- Time=2250 ns
		lsb_in <= transport std_logic_vector'("000000000001111"); --F
		-- --------------------
		WAIT FOR 150 ns; -- Time=2400 ns
		lsb_in <= transport std_logic_vector'("000000000010000"); --10
		-- --------------------
		WAIT FOR 12 ns; -- Time=2412 ns
		CHECK_msb_out("000000000000000",2412); --0
		CHECK_lsb_out("000000000010000",2412); --10
		-- --------------------
		WAIT FOR 138 ns; -- Time=2550 ns
		lsb_in <= transport std_logic_vector'("000000000010001"); --11
		-- --------------------
		WAIT FOR 150 ns; -- Time=2700 ns
		lsb_in <= transport std_logic_vector'("000000000010010"); --12
		-- --------------------
		WAIT FOR 12 ns; -- Time=2712 ns
		CHECK_msb_out("000000000000000",2712); --0
		CHECK_lsb_out("000000000010010",2712); --12
		-- --------------------
		WAIT FOR 138 ns; -- Time=2850 ns
		lsb_in <= transport std_logic_vector'("000000000010011"); --13
		-- --------------------
		WAIT FOR 150 ns; -- Time=3000 ns
		lsb_in <= transport std_logic_vector'("000000000010100"); --14
		-- --------------------
		WAIT FOR 12 ns; -- Time=3012 ns
		CHECK_msb_out("000000000000000",3012); --0
		CHECK_lsb_out("000000000010100",3012); --14
		-- --------------------
		WAIT FOR 138 ns; -- Time=3150 ns
		lsb_in <= transport std_logic_vector'("000000000010101"); --15
		-- --------------------
		WAIT FOR 150 ns; -- Time=3300 ns
		lsb_in <= transport std_logic_vector'("000000000010110"); --16
		-- --------------------
		WAIT FOR 12 ns; -- Time=3312 ns
		CHECK_msb_out("000000000000000",3312); --0
		CHECK_lsb_out("000000000010110",3312); --16
		-- --------------------
		WAIT FOR 138 ns; -- Time=3450 ns
		lsb_in <= transport std_logic_vector'("000000000010111"); --17
		-- --------------------
		WAIT FOR 150 ns; -- Time=3600 ns
		lsb_in <= transport std_logic_vector'("000000000011000"); --18
		-- --------------------
		WAIT FOR 12 ns; -- Time=3612 ns
		CHECK_msb_out("000000000000000",3612); --0
		CHECK_lsb_out("000000000011000",3612); --18
		-- --------------------
		WAIT FOR 138 ns; -- Time=3750 ns
		lsb_in <= transport std_logic_vector'("000000000011001"); --19
		-- --------------------
		WAIT FOR 150 ns; -- Time=3900 ns
		lsb_in <= transport std_logic_vector'("000000000011010"); --1A
		-- --------------------
		WAIT FOR 12 ns; -- Time=3912 ns
		CHECK_msb_out("000000000000000",3912); --0
		CHECK_lsb_out("000000000011010",3912); --1A
		-- --------------------
		WAIT FOR 138 ns; -- Time=4050 ns
		lsb_in <= transport std_logic_vector'("000000000011011"); --1B
		-- --------------------
		WAIT FOR 150 ns; -- Time=4200 ns
		lsb_in <= transport std_logic_vector'("000000000011100"); --1C
		-- --------------------
		WAIT FOR 12 ns; -- Time=4212 ns
		CHECK_msb_out("000000000000000",4212); --0
		CHECK_lsb_out("000000000011100",4212); --1C
		-- --------------------
		WAIT FOR 138 ns; -- Time=4350 ns
		lsb_in <= transport std_logic_vector'("000000000011101"); --1D
		-- --------------------
		WAIT FOR 150 ns; -- Time=4500 ns
		lsb_in <= transport std_logic_vector'("000000000011110"); --1E
		-- --------------------
		WAIT FOR 12 ns; -- Time=4512 ns
		CHECK_msb_out("000000000000000",4512); --0
		CHECK_lsb_out("000000000011110",4512); --1E
		-- --------------------
		WAIT FOR 138 ns; -- Time=4650 ns
		lsb_in <= transport std_logic_vector'("000000000011111"); --1F
		-- --------------------
		WAIT FOR 150 ns; -- Time=4800 ns
		lsb_in <= transport std_logic_vector'("000000000010000"); --10
		-- --------------------
		WAIT FOR 12 ns; -- Time=4812 ns
		CHECK_msb_out("000000000000000",4812); --0
		CHECK_lsb_out("000000000010000",4812); --10
		-- --------------------
		WAIT FOR 288 ns; -- Time=5100 ns
		lsb_in <= transport std_logic_vector'("000000000010001"); --11
		-- --------------------
		WAIT FOR 12 ns; -- Time=5112 ns
		CHECK_msb_out("000000000000000",5112); --0
		CHECK_lsb_out("000000000010001",5112); --11
		-- --------------------
		WAIT FOR 288 ns; -- Time=5400 ns
		lsb_in <= transport std_logic_vector'("000000000010010"); --12
		-- --------------------
		WAIT FOR 12 ns; -- Time=5412 ns
		CHECK_msb_out("000000000000000",5412); --0
		CHECK_lsb_out("000000000010010",5412); --12
		-- --------------------
		WAIT FOR 288 ns; -- Time=5700 ns
		lsb_in <= transport std_logic_vector'("000000000010011"); --13
		-- --------------------
		WAIT FOR 12 ns; -- Time=5712 ns
		CHECK_msb_out("000000000000000",5712); --0
		CHECK_lsb_out("000000000010011",5712); --13
		-- --------------------
		WAIT FOR 288 ns; -- Time=6000 ns
		lsb_in <= transport std_logic_vector'("000000000010100"); --14
		-- --------------------
		WAIT FOR 12 ns; -- Time=6012 ns
		CHECK_msb_out("000000000000000",6012); --0
		CHECK_lsb_out("000000000010100",6012); --14
		-- --------------------
		WAIT FOR 288 ns; -- Time=6300 ns
		lsb_in <= transport std_logic_vector'("000000000010101"); --15
		-- --------------------
		WAIT FOR 12 ns; -- Time=6312 ns
		CHECK_msb_out("000000000000000",6312); --0
		CHECK_lsb_out("000000000010101",6312); --15
		-- --------------------
		WAIT FOR 288 ns; -- Time=6600 ns
		lsb_in <= transport std_logic_vector'("000000000010110"); --16
		-- --------------------
		WAIT FOR 12 ns; -- Time=6612 ns
		CHECK_msb_out("000000000000000",6612); --0
		CHECK_lsb_out("000000000010110",6612); --16
		-- --------------------
		WAIT FOR 288 ns; -- Time=6900 ns
		lsb_in <= transport std_logic_vector'("000000000010111"); --17
		-- --------------------
		WAIT FOR 12 ns; -- Time=6912 ns
		CHECK_msb_out("000000000000000",6912); --0
		CHECK_lsb_out("000000000010111",6912); --17
		-- --------------------
		WAIT FOR 288 ns; -- Time=7200 ns
		lsb_in <= transport std_logic_vector'("000000000011000"); --18
		-- --------------------
		WAIT FOR 12 ns; -- Time=7212 ns
		CHECK_msb_out("000000000000000",7212); --0
		CHECK_lsb_out("000000000011000",7212); --18
		-- --------------------
		WAIT FOR 288 ns; -- Time=7500 ns
		lsb_in <= transport std_logic_vector'("000000000011001"); --19
		-- --------------------
		WAIT FOR 12 ns; -- Time=7512 ns
		CHECK_msb_out("000000000000000",7512); --0
		CHECK_lsb_out("000000000011001",7512); --19
		-- --------------------
		WAIT FOR 288 ns; -- Time=7800 ns
		lsb_in <= transport std_logic_vector'("000000000011010"); --1A
		-- --------------------
		WAIT FOR 12 ns; -- Time=7812 ns
		CHECK_msb_out("000000000000000",7812); --0
		CHECK_lsb_out("000000000011010",7812); --1A
		-- --------------------
		WAIT FOR 288 ns; -- Time=8100 ns
		lsb_in <= transport std_logic_vector'("000000000011011"); --1B
		-- --------------------
		WAIT FOR 12 ns; -- Time=8112 ns
		CHECK_msb_out("000000000000000",8112); --0
		CHECK_lsb_out("000000000011011",8112); --1B
		-- --------------------
		WAIT FOR 288 ns; -- Time=8400 ns
		lsb_in <= transport std_logic_vector'("000000000011100"); --1C
		-- --------------------
		WAIT FOR 12 ns; -- Time=8412 ns
		CHECK_msb_out("000000000000000",8412); --0
		CHECK_lsb_out("000000000011100",8412); --1C
		-- --------------------
		WAIT FOR 288 ns; -- Time=8700 ns
		lsb_in <= transport std_logic_vector'("000000000011101"); --1D
		-- --------------------
		WAIT FOR 12 ns; -- Time=8712 ns
		CHECK_msb_out("000000000000000",8712); --0
		CHECK_lsb_out("000000000011101",8712); --1D
		-- --------------------
		WAIT FOR 288 ns; -- Time=9000 ns
		lsb_in <= transport std_logic_vector'("000000000011110"); --1E
		-- --------------------
		WAIT FOR 12 ns; -- Time=9012 ns
		CHECK_msb_out("000000000000000",9012); --0
		CHECK_lsb_out("000000000011110",9012); --1E
		-- --------------------
		WAIT FOR 288 ns; -- Time=9300 ns
		lsb_in <= transport std_logic_vector'("000000000011111"); --1F
		-- --------------------
		WAIT FOR 12 ns; -- Time=9312 ns
		CHECK_msb_out("000000000000000",9312); --0
		CHECK_lsb_out("000000000011111",9312); --1F
		-- --------------------
		WAIT FOR 300 ns; -- Time=9612 ns
		CHECK_msb_out("000000000000000",9612); --0
		CHECK_lsb_out("000000000011111",9612); --1F
		-- --------------------
		WAIT FOR 300 ns; -- Time=9912 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION timelatch_cfg OF timelatch_tbw IS
	FOR testbench_arch
	END FOR;
END timelatch_cfg;