info x 323 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
col x 276 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 timelatch
term mark 129 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

var add 2 0 0 226 13 0 276 300 150 150 6 6 0 0 0 0 clkInstd_logicDUAL_EDGEclk
var add 1 0 0 98 12 0 276 150 75 75 6 6 0 0 0 0 resetInstd_logicDUAL_EDGEclk
var add 3 14 0 100 14 0 276 150 75 75 6 6 0 0 0 0 msb_inInstd_logic_vectorDUAL_EDGEclk
var add 4 14 0 100 15 0 276 150 75 75 6 6 0 0 0 0 lsb_inInstd_logic_vectorDUAL_EDGEclk
var add 5 14 0 100 16 0 276 150 75 75 6 6 0 0 0 0 msb_outOutstd_logic_vectorDUAL_EDGEclk
var add 6 14 0 100 17 0 276 150 75 75 6 6 0 0 0 0 lsb_outOutstd_logic_vectorDUAL_EDGEclk
vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
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time info 6 6 6 6 150 150 1 1 0 0 0 0 0 0 0 0 nsclk
font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
src mod 0 1188157130 29623595 0 0 0 0 0 0 0 0 0 0 0 0 0 timelatch.vhd
utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
cellenab off 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
grid off 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
com add 1 1 0 468 8 0 -67 0 0 0 0 0 0 0 0 0 Waveform created by
HDL Bencher 6.1i
Source = timelatch.vhd
Mon Mar 08 08:13:54 2004
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type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logicBITDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logicBITDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logicBITDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logicBITDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logic_vectorVECTORDOWNTO
opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk
Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1.00000000000000