-- C:\JFB\XILINX\MWD\WORK\EBEAM\EBEAM
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Mon Mar 08 08:35:41 2004

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY timelatch_tbw IS
END timelatch_tbw;

ARCHITECTURE testbench_arch OF timelatch_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\ebeam\ebeam\timelatch_tbw.ano";
	COMPONENT timelatch
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			msb_in : In  std_logic_vector (14 DOWNTO 0);
			lsb_in : In  std_logic_vector (14 DOWNTO 0);
			msb_out : Out  std_logic_vector (14 DOWNTO 0);
			lsb_out : Out  std_logic_vector (14 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL msb_in : std_logic_vector (14 DOWNTO 0);
	SIGNAL lsb_in : std_logic_vector (14 DOWNTO 0);
	SIGNAL msb_out : std_logic_vector (14 DOWNTO 0);
	SIGNAL lsb_out : std_logic_vector (14 DOWNTO 0);

BEGIN
	UUT : timelatch
	PORT MAP (
		reset => reset,
		clk => clk,
		msb_in => msb_in,
		lsb_in => lsb_in,
		msb_out => msb_out,
		lsb_out => lsb_out
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_msb_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",msb_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, msb_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_lsb_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",lsb_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, lsb_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		clk <= transport '1';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		ANNOTATE_msb_out(TX_TIME);
		ANNOTATE_lsb_out(TX_TIME);
		WAIT FOR 144 ns;
		TX_TIME := TX_TIME + 144;
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		WAIT FOR 138 ns;
		TX_TIME := TX_TIME + 138;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		msb_in <= transport std_logic_vector'("000000000000000"); --0
		lsb_in <= transport std_logic_vector'("000000000000000"); --0
		-- --------------------
		WAIT FOR 150 ns; -- Time=150 ns
		lsb_in <= transport std_logic_vector'("000000000000001"); --1
		-- --------------------
		WAIT FOR 150 ns; -- Time=300 ns
		reset <= transport '1';
		lsb_in <= transport std_logic_vector'("000000000000010"); --2
		-- --------------------
		WAIT FOR 150 ns; -- Time=450 ns
		lsb_in <= transport std_logic_vector'("000000000000011"); --3
		-- --------------------
		WAIT FOR 150 ns; -- Time=600 ns
		lsb_in <= transport std_logic_vector'("000000000000100"); --4
		-- --------------------
		WAIT FOR 150 ns; -- Time=750 ns
		lsb_in <= transport std_logic_vector'("000000000000101"); --5
		-- --------------------
		WAIT FOR 150 ns; -- Time=900 ns
		lsb_in <= transport std_logic_vector'("000000000000110"); --6
		-- --------------------
		WAIT FOR 150 ns; -- Time=1050 ns
		lsb_in <= transport std_logic_vector'("000000000000111"); --7
		-- --------------------
		WAIT FOR 150 ns; -- Time=1200 ns
		lsb_in <= transport std_logic_vector'("000000000001000"); --8
		-- --------------------
		WAIT FOR 150 ns; -- Time=1350 ns
		lsb_in <= transport std_logic_vector'("000000000001001"); --9
		-- --------------------
		WAIT FOR 150 ns; -- Time=1500 ns
		lsb_in <= transport std_logic_vector'("000000000001010"); --A
		-- --------------------
		WAIT FOR 150 ns; -- Time=1650 ns
		lsb_in <= transport std_logic_vector'("000000000001011"); --B
		-- --------------------
		WAIT FOR 150 ns; -- Time=1800 ns
		lsb_in <= transport std_logic_vector'("000000000001100"); --C
		-- --------------------
		WAIT FOR 150 ns; -- Time=1950 ns
		lsb_in <= transport std_logic_vector'("000000000001101"); --D
		-- --------------------
		WAIT FOR 150 ns; -- Time=2100 ns
		lsb_in <= transport std_logic_vector'("000000000001110"); --E
		-- --------------------
		WAIT FOR 150 ns; -- Time=2250 ns
		lsb_in <= transport std_logic_vector'("000000000001111"); --F
		-- --------------------
		WAIT FOR 150 ns; -- Time=2400 ns
		lsb_in <= transport std_logic_vector'("000000000010000"); --10
		-- --------------------
		WAIT FOR 150 ns; -- Time=2550 ns
		lsb_in <= transport std_logic_vector'("000000000010001"); --11
		-- --------------------
		WAIT FOR 150 ns; -- Time=2700 ns
		lsb_in <= transport std_logic_vector'("000000000010010"); --12
		-- --------------------
		WAIT FOR 150 ns; -- Time=2850 ns
		lsb_in <= transport std_logic_vector'("000000000010011"); --13
		-- --------------------
		WAIT FOR 150 ns; -- Time=3000 ns
		lsb_in <= transport std_logic_vector'("000000000010100"); --14
		-- --------------------
		WAIT FOR 150 ns; -- Time=3150 ns
		lsb_in <= transport std_logic_vector'("000000000010101"); --15
		-- --------------------
		WAIT FOR 150 ns; -- Time=3300 ns
		lsb_in <= transport std_logic_vector'("000000000010110"); --16
		-- --------------------
		WAIT FOR 150 ns; -- Time=3450 ns
		lsb_in <= transport std_logic_vector'("000000000010111"); --17
		-- --------------------
		WAIT FOR 150 ns; -- Time=3600 ns
		lsb_in <= transport std_logic_vector'("000000000011000"); --18
		-- --------------------
		WAIT FOR 150 ns; -- Time=3750 ns
		lsb_in <= transport std_logic_vector'("000000000011001"); --19
		-- --------------------
		WAIT FOR 150 ns; -- Time=3900 ns
		lsb_in <= transport std_logic_vector'("000000000011010"); --1A
		-- --------------------
		WAIT FOR 150 ns; -- Time=4050 ns
		lsb_in <= transport std_logic_vector'("000000000011011"); --1B
		-- --------------------
		WAIT FOR 150 ns; -- Time=4200 ns
		lsb_in <= transport std_logic_vector'("000000000011100"); --1C
		-- --------------------
		WAIT FOR 150 ns; -- Time=4350 ns
		lsb_in <= transport std_logic_vector'("000000000011101"); --1D
		-- --------------------
		WAIT FOR 150 ns; -- Time=4500 ns
		lsb_in <= transport std_logic_vector'("000000000011110"); --1E
		-- --------------------
		WAIT FOR 150 ns; -- Time=4650 ns
		lsb_in <= transport std_logic_vector'("000000000011111"); --1F
		-- --------------------
		WAIT FOR 150 ns; -- Time=4800 ns
		lsb_in <= transport std_logic_vector'("000000000010000"); --10
		-- --------------------
		WAIT FOR 300 ns; -- Time=5100 ns
		lsb_in <= transport std_logic_vector'("000000000010001"); --11
		-- --------------------
		WAIT FOR 300 ns; -- Time=5400 ns
		lsb_in <= transport std_logic_vector'("000000000010010"); --12
		-- --------------------
		WAIT FOR 300 ns; -- Time=5700 ns
		lsb_in <= transport std_logic_vector'("000000000010011"); --13
		-- --------------------
		WAIT FOR 300 ns; -- Time=6000 ns
		lsb_in <= transport std_logic_vector'("000000000010100"); --14
		-- --------------------
		WAIT FOR 300 ns; -- Time=6300 ns
		lsb_in <= transport std_logic_vector'("000000000010101"); --15
		-- --------------------
		WAIT FOR 300 ns; -- Time=6600 ns
		lsb_in <= transport std_logic_vector'("000000000010110"); --16
		-- --------------------
		WAIT FOR 300 ns; -- Time=6900 ns
		lsb_in <= transport std_logic_vector'("000000000010111"); --17
		-- --------------------
		WAIT FOR 300 ns; -- Time=7200 ns
		lsb_in <= transport std_logic_vector'("000000000011000"); --18
		-- --------------------
		WAIT FOR 300 ns; -- Time=7500 ns
		lsb_in <= transport std_logic_vector'("000000000011001"); --19
		-- --------------------
		WAIT FOR 300 ns; -- Time=7800 ns
		lsb_in <= transport std_logic_vector'("000000000011010"); --1A
		-- --------------------
		WAIT FOR 300 ns; -- Time=8100 ns
		lsb_in <= transport std_logic_vector'("000000000011011"); --1B
		-- --------------------
		WAIT FOR 300 ns; -- Time=8400 ns
		lsb_in <= transport std_logic_vector'("000000000011100"); --1C
		-- --------------------
		WAIT FOR 300 ns; -- Time=8700 ns
		lsb_in <= transport std_logic_vector'("000000000011101"); --1D
		-- --------------------
		WAIT FOR 300 ns; -- Time=9000 ns
		lsb_in <= transport std_logic_vector'("000000000011110"); --1E
		-- --------------------
		WAIT FOR 300 ns; -- Time=9300 ns
		lsb_in <= transport std_logic_vector'("000000000011111"); --1F
		-- --------------------
		WAIT FOR 612 ns; -- Time=9912 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION timelatch_cfg OF timelatch_tbw IS
	FOR testbench_arch
	END FOR;
END timelatch_cfg;