library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity timelatch_en is
    Port ( reset 		: in  std_logic;
           clk 		: in  std_logic;
			  enable		: in  std_logic;	  -- ebeam oe (ext buffer)
           msb_in 	: in  std_logic_vector(15 downto 0);
           lsb_in 	: in  std_logic_vector(15 downto 0);
           msb_out 	: out std_logic_vector(15 downto 0);
           lsb_out 	: out std_logic_vector(15 downto 0)			  
			  );
end timelatch_en;

architecture Behavioral of timelatch_en is

signal msb_internal: std_logic_vector(15 downto 0);
signal lsb_internal: std_logic_vector(15 downto 0);

begin

	msb_out	<= msb_internal;
	lsb_out	<= lsb_internal;

	process (reset, clk, enable, msb_in, lsb_in, msb_internal, lsb_internal)
	begin
		if reset = '0' then
			msb_internal <= "0000000000000000";
			lsb_internal <= "0000000000000000";

		elsif ( clk'event and clk = '1' ) then

			if enable = '1' then

				msb_internal <= msb_in;
				lsb_internal <= lsb_in;

			else
				msb_internal <= msb_internal;
				lsb_internal <= lsb_internal;

			end if;

		else
			msb_internal <= msb_internal;
			lsb_internal <= lsb_internal;

		end if;
	end process;

end Behavioral;