info x 246 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
radix x 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 edge_en
term mark 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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var add 1 0 0 98 22 0 257 240 120 120 4 4 0 0 0 0 resetInstd_logicRISING_EDGEtimeclk
var add 3 0 0 98 24 0 257 240 120 120 4 4 0 0 0 0 ebeamInstd_logicRISING_EDGEtimeclk
var add 4 0 0 98 25 0 257 240 120 120 4 4 0 0 0 0 riseOutstd_logicRISING_EDGEtimeclk
var add 5 0 0 98 26 0 257 240 120 120 4 4 0 0 0 0 fallOutstd_logicRISING_EDGEtimeclk
vdone xxx 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
npos xxx 75 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
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time info 6 6 4 4 120 120 1 1 0 0 0 0 0 0 0 0 nstimeclk
font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
src mod 0 719824650 29677725 0 0 0 0 0 0 0 0 0 0 0 0 0 edge_en.vhd
utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
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com add 1 0 2 364 7 0 -67 0 0 0 0 0 0 0 0 0 Waveform created by
HDL Bencher 6.1i
Source = edge_en.vhd
Thu Dec 02 10:24:35 2004
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