-- C:\JFB\XILINX\MWD\WORK\EBEAM\EBEAM
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Thu Dec 02 10:32:26 2004

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY edge_en_tbw IS
END edge_en_tbw;

ARCHITECTURE testbench_arch OF edge_en_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\ebeam\ebeam\edge_en_tbw.ano";
	COMPONENT edge_en
		PORT (
			reset : In  std_logic;
			timeclk : In  std_logic;
			ebeam : In  std_logic;
			rise : Out  std_logic;
			fall : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL timeclk : std_logic;
	SIGNAL ebeam : std_logic;
	SIGNAL rise : std_logic;
	SIGNAL fall : std_logic;

BEGIN
	UUT : edge_en
	PORT MAP (
		reset => reset,
		timeclk => timeclk,
		ebeam => ebeam,
		rise => rise,
		fall => fall
	);

	PROCESS -- clock process for timeclk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_rise(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rise,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rise);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_fall(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",fall,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, fall);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		timeclk <= transport '0';
		WAIT FOR 4 ns;
		TX_TIME := TX_TIME + 4;
		timeclk <= transport '1';
		WAIT FOR 4 ns;
		TX_TIME := TX_TIME + 4;
		ANNOTATE_rise(TX_TIME);
		ANNOTATE_fall(TX_TIME);
		WAIT FOR 116 ns;
		TX_TIME := TX_TIME + 116;
		timeclk <= transport '0';
		WAIT FOR 116 ns;
		TX_TIME := TX_TIME + 116;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for timeclk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		ebeam <= transport '0';
		-- --------------------
		WAIT FOR 240 ns; -- Time=240 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 240 ns; -- Time=480 ns
		ebeam <= transport '1';
		-- --------------------
		WAIT FOR 1440 ns; -- Time=1920 ns
		ebeam <= transport '0';
		-- --------------------
		WAIT FOR 2168 ns; -- Time=4088 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION edge_en_cfg OF edge_en_tbw IS
	FOR testbench_arch
	END FOR;
END edge_en_cfg;