library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;


-- ********************************************
-- ALL Signals are active LOW unless specified
-- ********************************************
-- 
-- rise and fall are active HIGH since the timelatch_en
-- works with enable =1
--
--

entity edge_en is
    Port ( reset 		: in std_logic;
           timeclk 	: in std_logic;
           ebeam 		: in std_logic;
           rise 		: out std_logic;
           fall 		: out std_logic);
end edge_en;

architecture Behavioral of edge_en is

-- Components
-------------------------------------------------------
	COMPONENT dff
	PORT(
		reset 	: IN std_logic;
		clk 		: IN std_logic;
		din 		: IN std_logic;          
		qout 		: OUT std_logic
		);
	END COMPONENT;

-- Signals
-------------------------------------------------------
	type state_TYPE is (s0, s1, s2, s3);
	attribute ENUM_ENCODING: STRING;
	attribute ENUM_ENCODING of state_TYPE: type is "000 001 010 011";

	signal state, next_state : state_TYPE;

	signal ebeam_sig : std_logic ; -- sync'd ebeam

begin

	Inst_dff: dff PORT MAP(
		reset 	=> reset,
		clk 		=> timeclk,
		din 		=> ebeam,
		qout 		=> ebeam_sig
	);

	----------------------------------------------------
	-- FSM sequence / definition	
	process (reset, timeclk)
	begin
		if reset = '0' then
			
				state <= s0;
		
		elsif (timeclk'event and timeclk= '1') then
		
				state <= next_state;
		
		else
				state <= state;
		end if;
	end process;
	----------------------------------------------------
	-- FSM Description
	process (state, ebeam_sig)
	begin
		case state is
			-------------------------
			when s0 =>	 -- Init

				rise <= '0';
				fall <= '0';

				if  ebeam_sig = '1' then
				
						next_state <= s1;
				
				else  next_state <= s0;
				
				end if;
				
			-------------------------
			-- 
			when s1 =>	-- latch counter content after rising edge

				rise <= '1';
				fall <= '0';

				next_state <= s2;
											
			-------------------------
			--
			when s2 =>	--  One sampling only !

				rise <= '0';
				fall <= '0';

				if  ebeam_sig = '0' then
				
						next_state <= s3;
				
				else  next_state <= s2;
				
				end if;

			-------------------------
			-- 
			when s3 =>	-- latch counter content after falling edge

				rise <= '0';
				fall <= '1';

				next_state <= s0;
				
			-------------------------
			when others =>

				rise <= '0';
				fall <= '0';

				next_state <= s0;

		end case;
    end process;
	----------------------------------------------------

end Behavioral;