info x 254 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
col x 257 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
radix x 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ebeammux
term mark 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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var add 1 0 0 98 12 0 257 4800 2400 2400 4 4 0 0 0 0 resetInstd_logicRISING_EDGEsysclk
var add 3 0 0 98 14 0 257 4800 2400 2400 4 4 0 0 0 0 timer1Instd_logicRISING_EDGEsysclk
var add 4 0 0 98 15 0 257 4800 2400 2400 4 4 0 0 0 0 timer2Instd_logicRISING_EDGEsysclk
var add 5 0 0 98 16 0 257 4800 2400 2400 4 4 0 0 0 0 upwordInstd_logicRISING_EDGEsysclk
var add 6 0 0 98 17 0 257 4800 2400 2400 4 4 0 0 0 0 lowordInstd_logicRISING_EDGEsysclk
var add 7 15 0 100 18 0 257 4800 2400 2400 4 4 0 0 0 0 msb1Instd_logic_vectorRISING_EDGEsysclk
var add 8 15 0 100 19 0 257 4800 2400 2400 4 4 0 0 0 0 lsb1Instd_logic_vectorRISING_EDGEsysclk
var add 9 15 0 100 20 0 257 4800 2400 2400 4 4 0 0 0 0 msb2Instd_logic_vectorRISING_EDGEsysclk
var add 10 15 0 100 21 0 257 4800 2400 2400 4 4 0 0 0 0 lsb2Instd_logic_vectorRISING_EDGEsysclk
var add 11 15 0 100 22 0 257 4800 2400 2400 4 4 0 0 0 0 muxoutOutstd_logic_vectorRISING_EDGEsysclk
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cell fill 11 70 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000000000100
cell fill 11 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000000000000100
time info 6 6 4 4 2400 2400 1 1 0 0 0 0 0 0 0 0 nssysclk
font save -14 0 400 49 0 0 0 0 0 0 0 0 0 0 0 0 Times New Roman
src mod 0 2079523044 29677711 0 0 0 0 0 0 0 0 0 0 0 0 0 ebeammux.vhd
utd false 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
cellenab off 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
grid off 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
com add 1 0 0 7248 13 0 -67 0 0 0 0 0 0 0 0 0 Waveform created by
HDL Bencher 6.1i
Source = ebeammux.vhd
Thu Dec 02 08:06:45 2004
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