library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ebeammux is
    Port ( timer1			: in 	std_logic;
			  timer2			: in 	std_logic;
			  upword			: in  std_logic;
			  loword			: in  std_logic;
			  msb1			: in 	std_logic_vector(15 downto 0);
	        lsb1 			: in 	std_logic_vector(15 downto 0);
 			  msb2			: in 	std_logic_vector(15 downto 0);
           lsb2 			: in 	std_logic_vector(15 downto 0);
           muxout 		: out std_logic_vector(15 downto 0)
           );
end ebeammux;

architecture Behavioral of ebeammux is

begin

	process (timer1, timer2, upword, loword, msb1, lsb1, msb2, lsb2)
	begin

			if 	( timer1 or upword )='0' then	muxout <= msb1;
			elsif ( timer1 or loword )='0' then	muxout <= lsb1;
			elsif ( timer2 or upword )='0' then	muxout <= msb2;
			elsif ( timer2 or loword )='0' then	muxout <= lsb2;
			else
				muxout  <= CONV_STD_LOGIC_VECTOR (0, 16); 
			end if;

 	end process;													  
end Behavioral;