-- C:\JFB\XILINX\MWD\WORK\EBEAM\EBEAM -- VHDL Annotation Test Bench created by -- HDL Bencher 6.1i -- Thu Dec 02 12:19:44 2004 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY ebeamctrl_tbw IS END ebeamctrl_tbw; ARCHITECTURE testbench_arch OF ebeamctrl_tbw IS -- If you get a compiler error on the following line, -- from the menu do Options->Configuration select VHDL 87 FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\ebeam\ebeam\ebeamctrl_tbw.ano"; COMPONENT ebeam_ctrl PORT ( reset : In std_logic; reset_timer : In std_logic; timeclk : In std_logic; sysclk : In std_logic; ebeam_oe : In std_logic; ebeam_sig : In std_logic; timer1 : In std_logic; timer2 : In std_logic; upword : In std_logic; loword : In std_logic; toto : Out std_logic_vector (15 DOWNTO 0); ebeam_data : Out std_logic_vector (15 DOWNTO 0) ); END COMPONENT; SIGNAL reset : std_logic; SIGNAL reset_timer : std_logic; SIGNAL timeclk : std_logic; SIGNAL sysclk : std_logic; SIGNAL ebeam_oe : std_logic; SIGNAL ebeam_sig : std_logic; SIGNAL timer1 : std_logic; SIGNAL timer2 : std_logic; SIGNAL upword : std_logic; SIGNAL loword : std_logic; SIGNAL toto : std_logic_vector (15 DOWNTO 0); SIGNAL ebeam_data : std_logic_vector (15 DOWNTO 0); BEGIN UUT : ebeam_ctrl PORT MAP ( reset => reset, reset_timer => reset_timer, timeclk => timeclk, sysclk => sysclk, ebeam_oe => ebeam_oe, ebeam_sig => ebeam_sig, timer1 => timer1, timer2 => timer2, upword => upword, loword => loword, toto => toto, ebeam_data => ebeam_data ); PROCESS -- clock process for sysclk, VARIABLE TX_TIME : INTEGER :=0; PROCEDURE ANNOTATE_ebeam_data( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC,string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'(",ebeam_data,")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ebeam_data); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; BEGIN CLOCK_LOOP : LOOP sysclk <= transport '0'; WAIT FOR 4 ns; TX_TIME := TX_TIME + 4; sysclk <= transport '1'; WAIT FOR 4 ns; TX_TIME := TX_TIME + 4; ANNOTATE_ebeam_data(TX_TIME); WAIT FOR 116 ns; TX_TIME := TX_TIME + 116; sysclk <= transport '0'; WAIT FOR 116 ns; TX_TIME := TX_TIME + 116; END LOOP CLOCK_LOOP; END PROCESS; PROCESS -- clock process for timeclk, VARIABLE TX_TIME : INTEGER :=0; PROCEDURE ANNOTATE_toto( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC,string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'(",toto,")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, toto); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; BEGIN CLOCK_LOOP : LOOP timeclk <= transport '0'; WAIT FOR 4 ns; TX_TIME := TX_TIME + 4; timeclk <= transport '1'; WAIT FOR 4 ns; TX_TIME := TX_TIME + 4; ANNOTATE_toto(TX_TIME); WAIT FOR 1916 ns; TX_TIME := TX_TIME + 1916; timeclk <= transport '0'; WAIT FOR 1916 ns; TX_TIME := TX_TIME + 1916; END LOOP CLOCK_LOOP; END PROCESS; PROCESS -- Process for sysclk VARIABLE TX_OUT : LINE; BEGIN -- -------------------- reset <= transport '0'; reset_timer <= transport '0'; timer1 <= transport '1'; timer2 <= transport '1'; upword <= transport '1'; loword <= transport '1'; -- -------------------- WAIT FOR 240 ns; -- Time=240 ns ebeam_oe <= transport '1'; -- -------------------- WAIT FOR 480 ns; -- Time=720 ns reset_timer <= transport '1'; -- -------------------- WAIT FOR 480 ns; -- Time=1200 ns reset <= transport '1'; -- -------------------- WAIT FOR 52560 ns; -- Time=53760 ns ebeam_oe <= transport '0'; -- -------------------- WAIT FOR 1440 ns; -- Time=55200 ns timer1 <= transport '0'; -- -------------------- WAIT FOR 480 ns; -- Time=55680 ns upword <= transport '0'; -- -------------------- WAIT FOR 1440 ns; -- Time=57120 ns upword <= transport '1'; -- -------------------- WAIT FOR 960 ns; -- Time=58080 ns loword <= transport '0'; -- -------------------- WAIT FOR 2160 ns; -- Time=60240 ns loword <= transport '1'; -- -------------------- WAIT FOR 1200 ns; -- Time=61440 ns timer1 <= transport '1'; -- -------------------- WAIT FOR 5280 ns; -- Time=66720 ns timer2 <= transport '0'; -- -------------------- WAIT FOR 484 ns; -- Time=67204 ns -- -------------------- STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; PROCESS -- Process for timeclk VARIABLE TX_OUT : LINE; BEGIN -- -------------------- -- -------------------- WAIT FOR 67204 ns; -- Time=67204 ns -- -------------------- STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; PROCESS -- Process for Asynchronous Signals VARIABLE TX_OUT : LINE; BEGIN -- -------------------- ebeam_sig <= transport '1'; -- -------------------- WAIT FOR 4 ns; -- Time=4 ns ebeam_sig <= transport '0'; -- -------------------- WAIT FOR 12 ns; -- Time=16 ns ebeam_sig <= transport '1'; -- -------------------- WAIT FOR 44659 ns; -- Time=44675 ns -- -------------------- WAIT FOR 22529 ns; -- Time=67204 ns -- -------------------- STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; END testbench_arch; CONFIGURATION ebeam_ctrl_cfg OF ebeamctrl_tbw IS FOR testbench_arch END FOR; END ebeam_ctrl_cfg;