library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ebeam_ctrl is
    Port ( reset 			: in  std_logic;
           reset_timer	: in  std_logic;
           timeclk		: in  std_logic;
           sysclk 		: in  std_logic;
			  ebeam_oe		: in  std_logic;	 -- from controller
           ebeam_sig 	: in  std_logic;	 -- true ebeam signal (input)
			  timer1			: in  std_logic;
			  timer2			: in  std_logic;
           upword 		: in  std_logic;
           loword 		: in  std_logic;
        ebeam_data 	: out std_logic_vector(15 downto 0));
end ebeam_ctrl;

architecture Behavioral of ebeam_ctrl is

	-------------------------------------------------------
	-- Components
	-------------------------------------------------------
	COMPONENT counter32
	PORT(
		reset 			: IN std_logic;
		clk 				: IN std_logic;
		msb_out 			: OUT std_logic_vector(15 downto 0);
		lsb_out 			: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
 	-------------------------------------------------------
	COMPONENT edge_en
	PORT(
		reset 			: IN std_logic;
		timeclk 			: IN std_logic;
		ebeam 			: IN std_logic;          
		rise 				: OUT std_logic;
		fall 				: OUT std_logic
		);
	END COMPONENT;
 	-------------------------------------------------------
	COMPONENT timelatch
	PORT(
		reset 			: IN std_logic;
		clk  				: IN std_logic;
		msb_in  			: IN std_logic_vector(15 downto 0);
		lsb_in  			: IN std_logic_vector(15 downto 0);          
		msb_out  		: OUT std_logic_vector(15 downto 0);
		lsb_out 			: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
 	-------------------------------------------------------
	COMPONENT timelatch_en
	PORT(
		reset 			: IN std_logic;
		clk 				: IN std_logic;
		enable 			: IN std_logic;
		msb_in 			: IN std_logic_vector(15 downto 0);
		lsb_in 			: IN std_logic_vector(15 downto 0);          
		msb_out 			: OUT std_logic_vector(15 downto 0);
		lsb_out 			: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
 	-------------------------------------------------------
	COMPONENT ebeammux
	PORT(
		timer1 			: IN std_logic;
		timer2 			: IN std_logic;
		upword 			: IN std_logic;
		loword 			: IN std_logic;
		msb1 				: IN std_logic_vector(15 downto 0);
		lsb1 				: IN std_logic_vector(15 downto 0);
		msb2 				: IN std_logic_vector(15 downto 0);
		lsb2 				: IN std_logic_vector(15 downto 0);          
		muxout 			: OUT std_logic_vector(15 downto 0)
		);
	END COMPONENT;
 	-------------------------------------------------------

 	-------------------------------------------------------
	-- Signals
	-------------------------------------------------------
	signal rst			: std_logic;

	signal cnt_msb		: std_logic_vector(15 downto 0);
	signal cnt_lsb		: std_logic_vector(15 downto 0);

	signal msb1			: std_logic_vector(15 downto 0);
	signal lsb1			: std_logic_vector(15 downto 0);
	signal msb2			: std_logic_vector(15 downto 0);
	signal lsb2			: std_logic_vector(15 downto 0);

	signal msbe1		: std_logic_vector(15 downto 0); -- from latch w/ en
	signal lsbe1		: std_logic_vector(15 downto 0);
	signal msbe2		: std_logic_vector(15 downto 0);
	signal lsbe2		: std_logic_vector(15 downto 0);

	signal rise			: std_logic;
	signal fall			: std_logic;

-------------------------------------------------------
-- Description
-------------------------------------------------------

begin

	rst 		<= reset and reset_timer;
	-------------------------------------------------------
	Inst_counter32: counter32 PORT MAP(
		reset 		=> rst,
		clk 			=> timeclk,
		msb_out 		=> cnt_msb,
		lsb_out 		=> cnt_lsb
	);
	-------------------------------------------------------
	Inst_edge_en: edge_en PORT MAP(
		reset 		=> rst,
		timeclk 		=> timeclk,
		ebeam 		=> ebeam_sig,
		rise 			=> rise,
		fall 			=> fall
	);
	-------------------------------------------------------
	-- latch on rising edge / timeclk
	Inst_timelatch_en1: timelatch_en PORT MAP(
		reset 		=> rst,
		clk 			=> timeclk,
		enable 		=> rise,
		msb_in 		=> cnt_msb,
		lsb_in 		=> cnt_lsb,
		msb_out 		=> msb1,
		lsb_out 		=> lsb1
	);
	-------------------------------------------------------
	-- latch on falling edge / timeclk
	Inst_timelatch_en2: timelatch_en PORT MAP(
		reset 		=> rst,
		clk 			=> timeclk,
		enable 		=> fall,
		msb_in 		=> cnt_msb,
		lsb_in 		=> cnt_lsb,
		msb_out 		=> msb2,
		lsb_out 		=> lsb2
	);
	-------------------------------------------------------
	Inst_timelatch_en3: timelatch_en PORT MAP(
		reset 		=> rst,
		clk 			=> sysclk,
		enable 		=> ebeam_oe,
		msb_in 		=> msb1,
		lsb_in 		=> lsb1,
		msb_out 		=> msbe1,
		lsb_out 		=> lsbe1
	);
	-------------------------------------------------------
	Inst_timelatch_en4: timelatch_en PORT MAP(
		reset 		=> rst,
		clk 			=> sysclk,
		enable 		=> ebeam_oe,
		msb_in 		=> msb2,
		lsb_in 		=> lsb2,
		msb_out 		=> msbe2,
		lsb_out 		=> lsbe2
	);
	-------------------------------------------------------
	Inst_ebeammux: ebeammux PORT MAP(
		timer1 		=> timer1,
		timer2 		=> timer2,
		upword 		=> upword,
		loword 		=> loword,
		msb1 			=> msbe1,
		lsb1 			=> lsbe1,
		msb2 			=> msbe2,
		lsb2 			=> lsbe2,
		muxout 		=> ebeam_data
	);
	-------------------------------------------------------

end Behavioral;