Release 6.1.03i - xst G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.72 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.72 s | Elapsed : 0.00 / 0.00 s --> Reading design: ebeam_ctrl.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : ebeam_ctrl.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : ebeam_ctrl Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : ebeam_ctrl Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Area Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : ebeam_ctrl.lso verilog2001 : YES Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 11 1-bit register : 1 16-bit register : 10 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : ebeam_ctrl.ngr Top Level Output File Name : ebeam_ctrl Output Format : NGC Optimization Goal : Area Keep Hierarchy : YES Target Technology : xc9500xl Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 26 Macro Statistics : # Registers : 176 # 1-bit register : 176 # Comparators : 2 # 16-bit comparator less : 2 # Xors : 30 # 1-bit xor2 : 30 Cell Usage : # BELS : 325 # AND2 : 163 # AND3 : 14 # INV : 67 # OR2 : 50 # OR3 : 1 # XOR2 : 30 # FlipFlops/Latches : 163 # FDC : 17 # FDCE : 144 # FTC : 2 # IO Buffers : 26 # IBUF : 10 # OBUF : 16 ========================================================================= CPU : 2.06 / 2.97 s | Elapsed : 2.00 / 3.00 s --> Total memory usage is 49720 kilobytes