cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: ebeam_ctrl Date: 3-14-2005, 12:07PM Device Used: XC95288XL-7-TQ144 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 180/288 ( 62%) 534 /1440 ( 37%) 163/288 ( 57%) 26 /117 ( 22%) 244/864 ( 28%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 8 8 | I/O : 23 86 Output : 16 16 | GCK/IO : 2 1 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 2 2 | GSR/IO : 1 0 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 26 26 MACROCELL RESOURCES: Total Macrocells Available 288 Registered Macrocells 163 Non-registered Macrocell driving I/O 16 GLOBAL RESOURCES: Signal 'timeclk' mapped onto global clock net GCK1. Signal 'sysclk' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. POWER DATA: There are 180 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 180 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State Inst_edge_en/ebeam_sig 2 2 FB6_4 STD (b) (b) RESET Inst_edge_en/state_FFT1 2 2 FB6_3 STD 136 I/O (b) RESET Inst_edge_en/state_FFT2 3 4 FB3_18 STD (b) (b) RESET cnt_lsb<0> 1 1 FB6_1 STD (b) (b) RESET cnt_lsb<10> 2 11 FB2_12 STD 15 I/O (b) RESET cnt_lsb<11> 2 12 FB2_11 STD (b) (b) RESET cnt_lsb<12> 2 13 FB2_10 STD 14 I/O (b) RESET cnt_lsb<13> 2 14 FB2_9 STD (b) (b) RESET cnt_lsb<14> 2 15 FB1_3 STD (b) (b) RESET cnt_lsb<15> 2 16 FB1_2 STD (b) (b) RESET cnt_lsb<1> 2 2 FB6_2 STD 135 I/O (b) RESET cnt_lsb<2> 2 3 FB2_8 STD 13 I/O (b) RESET cnt_lsb<3> 2 4 FB2_7 STD (b) (b) RESET cnt_lsb<4> 2 5 FB2_6 STD 12 I/O (b) RESET cnt_lsb<5> 2 6 FB2_5 STD 11 I/O (b) RESET cnt_lsb<6> 2 7 FB2_4 STD (b) (b) RESET cnt_lsb<7> 2 8 FB2_3 STD 10 I/O (b) RESET cnt_lsb<8> 2 9 FB2_2 STD 9 I/O (b) RESET cnt_lsb<9> 2 10 FB2_1 STD (b) (b) RESET cnt_msb<0> 2 17 FB1_1 STD (b) (b) RESET cnt_msb<10> 3 27 FB1_18 STD (b) (b) RESET cnt_msb<11> 3 28 FB1_17 STD 27 I/O (b) RESET cnt_msb<12> 3 29 FB1_16 STD (b) (b) RESET cnt_msb<13> 3 30 FB1_15 STD 26 I/O (b) RESET cnt_msb<14> 3 31 FB1_14 STD 25 I/O (b) RESET cnt_msb<15> 3 32 FB1_13 STD (b) (b) RESET cnt_msb<1> 3 18 FB1_12 STD 24 I/O (b) RESET cnt_msb<2> 3 19 FB1_11 STD (b) (b) RESET cnt_msb<3> 3 20 FB1_10 STD 23 I/O (b) RESET cnt_msb<4> 3 21 FB1_9 STD (b) (b) RESET cnt_msb<5> 3 22 FB1_8 STD 22 I/O (b) RESET cnt_msb<6> 3 23 FB1_7 STD (b) (b) RESET cnt_msb<7> 3 24 FB1_6 STD 21 I/O (b) RESET cnt_msb<8> 3 25 FB1_5 STD 20 I/O (b) RESET cnt_msb<9> 3 26 FB1_4 STD (b) (b) RESET ebeam_data<0> 4 8 FB14_15 STD FAST 107 I/O O ebeam_data<10> 4 8 FB16_10 STD FAST 96 I/O O ebeam_data<11> 4 8 FB16_8 STD FAST 95 I/O O ebeam_data<12> 4 8 FB16_6 STD FAST 94 I/O O ebeam_data<13> 4 8 FB16_5 STD FAST 93 I/O O ebeam_data<14> 4 8 FB16_3 STD FAST 92 I/O O ebeam_data<15> 4 8 FB16_2 STD FAST 91 I/O O ebeam_data<1> 4 8 FB14_14 STD FAST 106 I/O O ebeam_data<2> 4 8 FB14_11 STD FAST 105 I/O O ebeam_data<3> 4 8 FB14_10 STD FAST 104 I/O O ebeam_data<4> 4 8 FB14_8 STD FAST 103 I/O O ebeam_data<5> 4 8 FB14_6 STD FAST 102 I/O O ebeam_data<6> 4 8 FB14_5 STD FAST 101 I/O O ebeam_data<7> 4 8 FB14_3 STD FAST 100 I/O O ebeam_data<8> 4 8 FB16_12 STD FAST 98 I/O O ebeam_data<9> 4 8 FB16_11 STD FAST 97 I/O O lsb1<0> 3 4 FB2_18 STD (b) (b) RESET lsb1<10> 3 4 FB2_17 STD 19 I/O (b) RESET lsb1<11> 3 4 FB2_16 STD (b) (b) RESET lsb1<12> 3 4 FB2_15 STD 17 I/O (b) RESET lsb1<13> 3 4 FB3_17 STD (b) (b) RESET lsb1<14> 3 4 FB3_16 STD (b) (b) RESET lsb1<15> 3 4 FB3_15 STD 33 I/O (b) RESET lsb1<1> 3 4 FB2_14 STD 16 I/O (b) RESET lsb1<2> 3 4 FB2_13 STD (b) (b) RESET lsb1<3> 3 4 FB3_14 STD 32 GCK/I/O GCK RESET lsb1<4> 3 4 FB3_13 STD (b) (b) RESET lsb1<5> 3 4 FB3_12 STD 31 I/O (b) RESET lsb1<6> 3 4 FB3_11 STD (b) (b) RESET lsb1<7> 3 4 FB3_10 STD 30 GCK/I/O GCK RESET lsb1<8> 3 4 FB3_9 STD (b) (b) RESET lsb1<9> 3 4 FB4_18 STD (b) (b) RESET lsb2<0> 3 4 FB4_17 STD (b) (b) RESET lsb2<10> 3 4 FB4_16 STD (b) (b) RESET lsb2<11> 3 4 FB4_15 STD (b) (b) RESET lsb2<12> 3 4 FB4_14 STD 7 I/O (b) RESET lsb2<13> 3 4 FB3_8 STD (b) (b) RESET lsb2<14> 3 4 FB3_7 STD (b) (b) RESET lsb2<15> 3 4 FB3_6 STD (b) (b) RESET lsb2<1> 3 4 FB4_13 STD (b) (b) RESET lsb2<2> 3 4 FB4_12 STD 6 GTS/I/O (b) RESET lsb2<3> 3 4 FB3_5 STD (b) (b) RESET lsb2<4> 3 4 FB3_4 STD (b) (b) RESET lsb2<5> 3 4 FB3_3 STD (b) (b) RESET lsb2<6> 3 4 FB3_2 STD 28 I/O (b) RESET lsb2<7> 3 4 FB3_1 STD (b) (b) RESET lsb2<8> 3 4 FB4_11 STD (b) (b) RESET lsb2<9> 3 4 FB4_10 STD (b) (b) RESET lsbe1<0> 3 3 FB6_18 STD (b) (b) RESET lsbe1<10> 3 3 FB6_17 STD (b) (b) RESET lsbe1<11> 3 3 FB6_16 STD (b) (b) RESET lsbe1<12> 3 3 FB6_15 STD 143 GSR/I/O I RESET lsbe1<13> 3 3 FB6_14 STD 142 I/O I RESET lsbe1<14> 3 3 FB6_13 STD (b) (b) RESET lsbe1<15> 3 3 FB6_12 STD (b) (b) RESET lsbe1<1> 3 3 FB6_11 STD (b) (b) RESET lsbe1<2> 3 3 FB6_10 STD 140 I/O (b) RESET lsbe1<3> 3 3 FB7_18 STD (b) (b) RESET lsbe1<4> 3 3 FB7_17 STD (b) (b) RESET lsbe1<5> 3 3 FB7_16 STD (b) (b) RESET lsbe1<6> 3 3 FB7_15 STD 49 I/O (b) RESET lsbe1<7> 3 3 FB7_14 STD (b) (b) RESET lsbe1<8> 3 3 FB7_13 STD (b) (b) RESET lsbe1<9> 3 3 FB7_12 STD 48 I/O (b) RESET lsbe2<0> 3 3 FB7_11 STD (b) (b) RESET lsbe2<10> 3 3 FB7_10 STD (b) (b) RESET lsbe2<11> 3 3 FB7_9 STD (b) (b) RESET lsbe2<12> 3 3 FB7_8 STD (b) (b) RESET lsbe2<13> 3 3 FB7_7 STD (b) (b) RESET lsbe2<14> 3 3 FB7_6 STD (b) (b) RESET lsbe2<15> 3 3 FB7_5 STD 46 I/O (b) RESET lsbe2<1> 3 3 FB7_4 STD (b) (b) RESET lsbe2<2> 3 3 FB7_3 STD 45 I/O (b) RESET lsbe2<3> 3 3 FB7_2 STD (b) (b) RESET lsbe2<4> 3 3 FB7_1 STD (b) (b) RESET lsbe2<5> 3 3 FB8_18 STD (b) (b) RESET lsbe2<6> 3 3 FB8_17 STD (b) (b) RESET lsbe2<7> 3 3 FB8_16 STD (b) (b) RESET lsbe2<8> 3 3 FB8_15 STD (b) (b) RESET lsbe2<9> 3 3 FB8_14 STD (b) (b) RESET msb1<0> 3 4 FB4_9 STD (b) (b) RESET msb1<10> 3 4 FB4_8 STD 5 GTS/I/O (b) RESET msb1<11> 3 4 FB4_7 STD (b) (b) RESET msb1<12> 3 4 FB4_6 STD 4 I/O (b) RESET msb1<13> 3 4 FB4_5 STD 3 GTS/I/O (b) RESET msb1<14> 3 4 FB5_18 STD (b) (b) RESET msb1<15> 3 4 FB5_17 STD 44 I/O (b) RESET msb1<1> 3 4 FB5_16 STD (b) (b) RESET msb1<2> 3 4 FB5_15 STD 43 I/O (b) RESET msb1<3> 3 4 FB5_14 STD 41 I/O (b) RESET msb1<4> 3 4 FB5_13 STD (b) (b) RESET msb1<5> 3 4 FB5_12 STD 40 I/O I RESET msb1<6> 3 4 FB5_11 STD (b) (b) RESET msb1<7> 3 4 FB5_10 STD 39 I/O (b) RESET msb1<8> 3 4 FB6_9 STD (b) (b) RESET msb1<9> 3 4 FB6_8 STD 139 I/O (b) RESET msb2<0> 3 4 FB4_4 STD (b) (b) RESET msb2<10> 3 4 FB4_3 STD (b) (b) RESET msb2<11> 3 4 FB4_2 STD 2 GTS/I/O (b) RESET msb2<12> 3 4 FB4_1 STD (b) (b) RESET msb2<13> 3 4 FB6_7 STD (b) (b) RESET msb2<14> 3 4 FB5_9 STD (b) (b) RESET msb2<15> 3 4 FB5_8 STD 38 GCK/I/O (b) RESET msb2<1> 3 4 FB5_7 STD (b) (b) RESET msb2<2> 3 4 FB5_6 STD (b) (b) RESET msb2<3> 3 4 FB5_5 STD 35 I/O (b) RESET msb2<4> 3 4 FB5_4 STD (b) (b) RESET msb2<5> 3 4 FB5_3 STD (b) (b) RESET msb2<6> 3 4 FB5_2 STD 34 I/O (b) RESET msb2<7> 3 4 FB5_1 STD (b) (b) RESET msb2<8> 3 4 FB6_6 STD 138 I/O (b) RESET msb2<9> 3 4 FB6_5 STD 137 I/O (b) RESET msbe1<0> 3 3 FB8_13 STD (b) (b) RESET msbe1<10> 3 3 FB8_12 STD (b) (b) RESET msbe1<11> 3 3 FB8_11 STD (b) (b) RESET msbe1<12> 3 3 FB8_10 STD 134 I/O (b) RESET msbe1<13> 3 3 FB8_9 STD (b) (b) RESET msbe1<14> 3 3 FB8_8 STD 133 I/O (b) RESET msbe1<15> 3 3 FB8_7 STD (b) (b) RESET msbe1<1> 3 3 FB8_6 STD (b) (b) RESET msbe1<2> 3 3 FB8_5 STD 132 I/O (b) RESET msbe1<3> 3 3 FB8_4 STD (b) (b) RESET msbe1<4> 3 3 FB8_3 STD 131 I/O (b) RESET msbe1<5> 3 3 FB8_2 STD 130 I/O (b) RESET msbe1<6> 3 3 FB8_1 STD (b) (b) RESET msbe1<7> 3 3 FB9_18 STD (b) (b) RESET msbe1<8> 3 3 FB9_17 STD 59 I/O (b) RESET msbe1<9> 3 3 FB9_16 STD (b) (b) RESET msbe2<0> 3 3 FB9_15 STD (b) (b) RESET msbe2<10> 3 3 FB9_14 STD 58 I/O (b) RESET msbe2<11> 3 3 FB9_13 STD (b) (b) RESET msbe2<12> 3 3 FB9_12 STD 57 I/O (b) RESET msbe2<13> 3 3 FB9_11 STD 56 I/O (b) RESET msbe2<14> 3 3 FB9_10 STD (b) (b) RESET msbe2<15> 3 3 FB9_9 STD (b) (b) RESET msbe2<1> 3 3 FB9_8 STD 54 I/O (b) RESET msbe2<2> 3 3 FB9_7 STD (b) (b) RESET msbe2<3> 3 3 FB9_6 STD 53 I/O (b) RESET msbe2<4> 3 3 FB9_5 STD 52 I/O (b) RESET msbe2<5> 3 3 FB9_4 STD (b) (b) RESET msbe2<6> 3 3 FB9_3 STD 51 I/O (b) RESET msbe2<7> 3 3 FB9_2 STD 50 I/O (b) RESET msbe2<8> 3 3 FB9_1 STD (b) (b) RESET msbe2<9> 3 3 FB10_18 STD (b) (b) RESET msbe2<9>/msbe2<9>_RSTF__$INT 1 2 FB10_17 STD 129 I/O (b) ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use ebeam_oe FB13_17 78 I/O I ebeam_sig FB5_12 40 I/O I loword FB15_10 82 I/O I reset FB6_15 143 GSR/I/O I reset_timer FB6_14 142 I/O I sysclk FB3_14 32 GCK/I/O GCK timeclk FB3_10 30 GCK/I/O GCK timer1 FB15_2 79 I/O I timer2 FB15_3 80 I/O I upword FB15_8 81 I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 18 32 32 51 0/0 8 FB2 18 16 16 42 0/0 10 FB3 18 13 13 54 0/0 5 FB4 18 16 16 54 0/0 6 FB5 18 12 12 54 0/0 8 FB6 18 18 18 49 0/0 8 FB7 18 20 20 54 0/0 4 FB8 18 20 20 54 0/0 5 FB9 18 20 20 54 0/0 9 FB10 2 5 5 4 0/0 10 FB11 0 0 0 0 0/0 7 FB12 0 0 0 0 0/0 6 FB13 0 0 0 0 0/0 6 FB14 8 36 36 32 8/0 8 FB15 0 0 0 0 0/0 9 FB16 8 36 36 32 8/0 8 ---- ----- ----- ----- 180 534 16/0 117 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use cnt_msb<0> 2 0 0 3 FB1_1 STD (b) (b) cnt_lsb<15> 2 0 0 3 FB1_2 STD (b) (b) cnt_lsb<14> 2 0 0 3 FB1_3 STD (b) (b) cnt_msb<9> 3 0 0 2 FB1_4 STD (b) (b) cnt_msb<8> 3 0 0 2 FB1_5 STD 20 I/O (b) cnt_msb<7> 3 0 0 2 FB1_6 STD 21 I/O (b) cnt_msb<6> 3 0 0 2 FB1_7 STD (b) (b) cnt_msb<5> 3 0 0 2 FB1_8 STD 22 I/O (b) cnt_msb<4> 3 0 0 2 FB1_9 STD (b) (b) cnt_msb<3> 3 0 0 2 FB1_10 STD 23 I/O (b) cnt_msb<2> 3 0 0 2 FB1_11 STD (b) (b) cnt_msb<1> 3 0 0 2 FB1_12 STD 24 I/O (b) cnt_msb<15> 3 0 0 2 FB1_13 STD (b) (b) cnt_msb<14> 3 0 0 2 FB1_14 STD 25 I/O (b) cnt_msb<13> 3 0 0 2 FB1_15 STD 26 I/O (b) cnt_msb<12> 3 0 0 2 FB1_16 STD (b) (b) cnt_msb<11> 3 0 0 2 FB1_17 STD 27 I/O (b) cnt_msb<10> 3 0 0 2 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: cnt_lsb<0> 12: cnt_lsb<5> 23: cnt_msb<1> 2: cnt_lsb<10> 13: cnt_lsb<6> 24: cnt_msb<2> 3: cnt_lsb<11> 14: cnt_lsb<7> 25: cnt_msb<3> 4: cnt_lsb<12> 15: cnt_lsb<8> 26: cnt_msb<4> 5: cnt_lsb<13> 16: cnt_lsb<9> 27: cnt_msb<5> 6: cnt_lsb<14> 17: cnt_msb<0> 28: cnt_msb<6> 7: cnt_lsb<15> 18: cnt_msb<10> 29: cnt_msb<7> 8: cnt_lsb<1> 19: cnt_msb<11> 30: cnt_msb<8> 9: cnt_lsb<2> 20: cnt_msb<12> 31: cnt_msb<9> 10: cnt_lsb<3> 21: cnt_msb<13> 32: msbe2<9>/msbe2<9>_RSTF__$INT 11: cnt_lsb<4> 22: cnt_msb<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs cnt_msb<0> XXXXXXXXXXXXXXXX...............X........ 17 17 cnt_lsb<15> XXXXXX.XXXXXXXXX...............X........ 16 16 cnt_lsb<14> XXXXX..XXXXXXXXX...............X........ 15 15 cnt_msb<9> XXXXXXXXXXXXXXXXX.....XXXXXXXX.X........ 26 26 cnt_msb<8> XXXXXXXXXXXXXXXXX.....XXXXXXX..X........ 25 25 cnt_msb<7> XXXXXXXXXXXXXXXXX.....XXXXXX...X........ 24 24 cnt_msb<6> XXXXXXXXXXXXXXXXX.....XXXXX....X........ 23 23 cnt_msb<5> XXXXXXXXXXXXXXXXX.....XXXX.....X........ 22 22 cnt_msb<4> XXXXXXXXXXXXXXXXX.....XXX......X........ 21 21 cnt_msb<3> XXXXXXXXXXXXXXXXX.....XX.......X........ 20 20 cnt_msb<2> XXXXXXXXXXXXXXXXX.....X........X........ 19 19 cnt_msb<1> XXXXXXXXXXXXXXXXX..............X........ 18 18 cnt_msb<15> XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX........ 32 32 cnt_msb<14> XXXXXXXXXXXXXXXXXXXXX.XXXXXXXXXX........ 31 31 cnt_msb<13> XXXXXXXXXXXXXXXXXXXX..XXXXXXXXXX........ 30 30 cnt_msb<12> XXXXXXXXXXXXXXXXXXX...XXXXXXXXXX........ 29 29 cnt_msb<11> XXXXXXXXXXXXXXXXXX....XXXXXXXXXX........ 28 28 cnt_msb<10> XXXXXXXXXXXXXXXXX.....XXXXXXXXXX........ 27 27 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use cnt_lsb<9> 2 0 0 3 FB2_1 STD (b) (b) cnt_lsb<8> 2 0 0 3 FB2_2 STD 9 I/O (b) cnt_lsb<7> 2 0 0 3 FB2_3 STD 10 I/O (b) cnt_lsb<6> 2 0 0 3 FB2_4 STD (b) (b) cnt_lsb<5> 2 0 0 3 FB2_5 STD 11 I/O (b) cnt_lsb<4> 2 0 0 3 FB2_6 STD 12 I/O (b) cnt_lsb<3> 2 0 0 3 FB2_7 STD (b) (b) cnt_lsb<2> 2 0 0 3 FB2_8 STD 13 I/O (b) cnt_lsb<13> 2 0 0 3 FB2_9 STD (b) (b) cnt_lsb<12> 2 0 0 3 FB2_10 STD 14 I/O (b) cnt_lsb<11> 2 0 0 3 FB2_11 STD (b) (b) cnt_lsb<10> 2 0 0 3 FB2_12 STD 15 I/O (b) lsb1<2> 3 0 0 2 FB2_13 STD (b) (b) lsb1<1> 3 0 0 2 FB2_14 STD 16 I/O (b) lsb1<12> 3 0 0 2 FB2_15 STD 17 I/O (b) lsb1<11> 3 0 0 2 FB2_16 STD (b) (b) lsb1<10> 3 0 0 2 FB2_17 STD 19 I/O (b) lsb1<0> 3 0 0 2 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_edge_en/state_FFT1 7: cnt_lsb<1> 12: cnt_lsb<6> 2: Inst_edge_en/state_FFT2 8: cnt_lsb<2> 13: cnt_lsb<7> 3: cnt_lsb<0> 9: cnt_lsb<3> 14: cnt_lsb<8> 4: cnt_lsb<10> 10: cnt_lsb<4> 15: cnt_lsb<9> 5: cnt_lsb<11> 11: cnt_lsb<5> 16: msbe2<9>/msbe2<9>_RSTF__$INT 6: cnt_lsb<12> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs cnt_lsb<9> ..X...XXXXXXXX.X........................ 10 10 cnt_lsb<8> ..X...XXXXXXX..X........................ 9 9 cnt_lsb<7> ..X...XXXXXX...X........................ 8 8 cnt_lsb<6> ..X...XXXXX....X........................ 7 7 cnt_lsb<5> ..X...XXXX.....X........................ 6 6 cnt_lsb<4> ..X...XXX......X........................ 5 5 cnt_lsb<3> ..X...XX.......X........................ 4 4 cnt_lsb<2> ..X...X........X........................ 3 3 cnt_lsb<13> ..XXXXXXXXXXXXXX........................ 14 14 cnt_lsb<12> ..XXX.XXXXXXXXXX........................ 13 13 cnt_lsb<11> ..XX..XXXXXXXXXX........................ 12 12 cnt_lsb<10> ..X...XXXXXXXXXX........................ 11 11 lsb1<2> XX.....X.......X........................ 4 4 lsb1<1> XX....X........X........................ 4 4 lsb1<12> XX...X.........X........................ 4 4 lsb1<11> XX..X..........X........................ 4 4 lsb1<10> XX.X...........X........................ 4 4 lsb1<0> XXX............X........................ 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use lsb2<7> 3 0 0 2 FB3_1 STD (b) (b) lsb2<6> 3 0 0 2 FB3_2 STD 28 I/O (b) lsb2<5> 3 0 0 2 FB3_3 STD (b) (b) lsb2<4> 3 0 0 2 FB3_4 STD (b) (b) lsb2<3> 3 0 0 2 FB3_5 STD (b) (b) lsb2<15> 3 0 0 2 FB3_6 STD (b) (b) lsb2<14> 3 0 0 2 FB3_7 STD (b) (b) lsb2<13> 3 0 0 2 FB3_8 STD (b) (b) lsb1<8> 3 0 0 2 FB3_9 STD (b) (b) lsb1<7> 3 0 0 2 FB3_10 STD 30 GCK/I/O GCK lsb1<6> 3 0 0 2 FB3_11 STD (b) (b) lsb1<5> 3 0 0 2 FB3_12 STD 31 I/O (b) lsb1<4> 3 0 0 2 FB3_13 STD (b) (b) lsb1<3> 3 0 0 2 FB3_14 STD 32 GCK/I/O GCK lsb1<15> 3 0 0 2 FB3_15 STD 33 I/O (b) lsb1<14> 3 0 0 2 FB3_16 STD (b) (b) lsb1<13> 3 0 0 2 FB3_17 STD (b) (b) Inst_edge_en/state_FFT2 3 0 0 2 FB3_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_edge_en/ebeam_sig 6: cnt_lsb<15> 10: cnt_lsb<6> 2: Inst_edge_en/state_FFT1 7: cnt_lsb<3> 11: cnt_lsb<7> 3: Inst_edge_en/state_FFT2 8: cnt_lsb<4> 12: cnt_lsb<8> 4: cnt_lsb<13> 9: cnt_lsb<5> 13: msbe2<9>/msbe2<9>_RSTF__$INT 5: cnt_lsb<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb2<7> .XX.......X.X........................... 4 4 lsb2<6> .XX......X..X........................... 4 4 lsb2<5> .XX.....X...X........................... 4 4 lsb2<4> .XX....X....X........................... 4 4 lsb2<3> .XX...X.....X........................... 4 4 lsb2<15> .XX..X......X........................... 4 4 lsb2<14> .XX.X.......X........................... 4 4 lsb2<13> .XXX........X........................... 4 4 lsb1<8> .XX........XX........................... 4 4 lsb1<7> .XX.......X.X........................... 4 4 lsb1<6> .XX......X..X........................... 4 4 lsb1<5> .XX.....X...X........................... 4 4 lsb1<4> .XX....X....X........................... 4 4 lsb1<3> .XX...X.....X........................... 4 4 lsb1<15> .XX..X......X........................... 4 4 lsb1<14> .XX.X.......X........................... 4 4 lsb1<13> .XXX........X........................... 4 4 Inst_edge_en/state_FFT2 XXX.........X........................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use msb2<12> 3 0 0 2 FB4_1 STD (b) (b) msb2<11> 3 0 0 2 FB4_2 STD 2 GTS/I/O (b) msb2<10> 3 0 0 2 FB4_3 STD (b) (b) msb2<0> 3 0 0 2 FB4_4 STD (b) (b) msb1<13> 3 0 0 2 FB4_5 STD 3 GTS/I/O (b) msb1<12> 3 0 0 2 FB4_6 STD 4 I/O (b) msb1<11> 3 0 0 2 FB4_7 STD (b) (b) msb1<10> 3 0 0 2 FB4_8 STD 5 GTS/I/O (b) msb1<0> 3 0 0 2 FB4_9 STD (b) (b) lsb2<9> 3 0 0 2 FB4_10 STD (b) (b) lsb2<8> 3 0 0 2 FB4_11 STD (b) (b) lsb2<2> 3 0 0 2 FB4_12 STD 6 GTS/I/O (b) lsb2<1> 3 0 0 2 FB4_13 STD (b) (b) lsb2<12> 3 0 0 2 FB4_14 STD 7 I/O (b) lsb2<11> 3 0 0 2 FB4_15 STD (b) (b) lsb2<10> 3 0 0 2 FB4_16 STD (b) (b) lsb2<0> 3 0 0 2 FB4_17 STD (b) (b) lsb1<9> 3 0 0 2 FB4_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_edge_en/state_FFT1 7: cnt_lsb<1> 12: cnt_msb<10> 2: Inst_edge_en/state_FFT2 8: cnt_lsb<2> 13: cnt_msb<11> 3: cnt_lsb<0> 9: cnt_lsb<8> 14: cnt_msb<12> 4: cnt_lsb<10> 10: cnt_lsb<9> 15: cnt_msb<13> 5: cnt_lsb<11> 11: cnt_msb<0> 16: msbe2<9>/msbe2<9>_RSTF__$INT 6: cnt_lsb<12> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb2<12> XX...........X.X........................ 4 4 msb2<11> XX..........X..X........................ 4 4 msb2<10> XX.........X...X........................ 4 4 msb2<0> XX........X....X........................ 4 4 msb1<13> XX............XX........................ 4 4 msb1<12> XX...........X.X........................ 4 4 msb1<11> XX..........X..X........................ 4 4 msb1<10> XX.........X...X........................ 4 4 msb1<0> XX........X....X........................ 4 4 lsb2<9> XX.......X.....X........................ 4 4 lsb2<8> XX......X......X........................ 4 4 lsb2<2> XX.....X.......X........................ 4 4 lsb2<1> XX....X........X........................ 4 4 lsb2<12> XX...X.........X........................ 4 4 lsb2<11> XX..X..........X........................ 4 4 lsb2<10> XX.X...........X........................ 4 4 lsb2<0> XXX............X........................ 4 4 lsb1<9> XX.......X.....X........................ 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 12/42 Number of signals used by logic mapping into function block: 12 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use msb2<7> 3 0 0 2 FB5_1 STD (b) (b) msb2<6> 3 0 0 2 FB5_2 STD 34 I/O (b) msb2<5> 3 0 0 2 FB5_3 STD (b) (b) msb2<4> 3 0 0 2 FB5_4 STD (b) (b) msb2<3> 3 0 0 2 FB5_5 STD 35 I/O (b) msb2<2> 3 0 0 2 FB5_6 STD (b) (b) msb2<1> 3 0 0 2 FB5_7 STD (b) (b) msb2<15> 3 0 0 2 FB5_8 STD 38 GCK/I/O (b) msb2<14> 3 0 0 2 FB5_9 STD (b) (b) msb1<7> 3 0 0 2 FB5_10 STD 39 I/O (b) msb1<6> 3 0 0 2 FB5_11 STD (b) (b) msb1<5> 3 0 0 2 FB5_12 STD 40 I/O I msb1<4> 3 0 0 2 FB5_13 STD (b) (b) msb1<3> 3 0 0 2 FB5_14 STD 41 I/O (b) msb1<2> 3 0 0 2 FB5_15 STD 43 I/O (b) msb1<1> 3 0 0 2 FB5_16 STD (b) (b) msb1<15> 3 0 0 2 FB5_17 STD 44 I/O (b) msb1<14> 3 0 0 2 FB5_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_edge_en/state_FFT1 5: cnt_msb<1> 9: cnt_msb<5> 2: Inst_edge_en/state_FFT2 6: cnt_msb<2> 10: cnt_msb<6> 3: cnt_msb<14> 7: cnt_msb<3> 11: cnt_msb<7> 4: cnt_msb<15> 8: cnt_msb<4> 12: msbe2<9>/msbe2<9>_RSTF__$INT Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb2<7> XX........XX............................ 4 4 msb2<6> XX.......X.X............................ 4 4 msb2<5> XX......X..X............................ 4 4 msb2<4> XX.....X...X............................ 4 4 msb2<3> XX....X....X............................ 4 4 msb2<2> XX...X.....X............................ 4 4 msb2<1> XX..X......X............................ 4 4 msb2<15> XX.X.......X............................ 4 4 msb2<14> XXX........X............................ 4 4 msb1<7> XX........XX............................ 4 4 msb1<6> XX.......X.X............................ 4 4 msb1<5> XX......X..X............................ 4 4 msb1<4> XX.....X...X............................ 4 4 msb1<3> XX....X....X............................ 4 4 msb1<2> XX...X.....X............................ 4 4 msb1<1> XX..X......X............................ 4 4 msb1<15> XX.X.......X............................ 4 4 msb1<14> XXX........X............................ 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use cnt_lsb<0> 1 0 0 4 FB6_1 STD (b) (b) cnt_lsb<1> 2 0 0 3 FB6_2 STD 135 I/O (b) Inst_edge_en/state_FFT1 2 0 0 3 FB6_3 STD 136 I/O (b) Inst_edge_en/ebeam_sig 2 0 0 3 FB6_4 STD (b) (b) msb2<9> 3 0 0 2 FB6_5 STD 137 I/O (b) msb2<8> 3 0 0 2 FB6_6 STD 138 I/O (b) msb2<13> 3 0 0 2 FB6_7 STD (b) (b) msb1<9> 3 0 0 2 FB6_8 STD 139 I/O (b) msb1<8> 3 0 0 2 FB6_9 STD (b) (b) lsbe1<2> 3 0 0 2 FB6_10 STD 140 I/O (b) lsbe1<1> 3 0 0 2 FB6_11 STD (b) (b) lsbe1<15> 3 0 0 2 FB6_12 STD (b) (b) lsbe1<14> 3 0 0 2 FB6_13 STD (b) (b) lsbe1<13> 3 0 0 2 FB6_14 STD 142 I/O I lsbe1<12> 3 0 0 2 FB6_15 STD 143 GSR/I/O I lsbe1<11> 3 0 0 2 FB6_16 STD (b) (b) lsbe1<10> 3 0 0 2 FB6_17 STD (b) (b) lsbe1<0> 3 0 0 2 FB6_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_edge_en/state_FFT1 7: ebeam_oe 13: lsb1<13> 2: Inst_edge_en/state_FFT2 8: ebeam_sig 14: lsb1<14> 3: cnt_lsb<0> 9: lsb1<0> 15: lsb1<15> 4: cnt_msb<13> 10: lsb1<10> 16: lsb1<1> 5: cnt_msb<8> 11: lsb1<11> 17: lsb1<2> 6: cnt_msb<9> 12: lsb1<12> 18: msbe2<9>/msbe2<9>_RSTF__$INT Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs cnt_lsb<0> .................X...................... 1 1 cnt_lsb<1> ..X..............X...................... 2 2 Inst_edge_en/state_FFT1 .X...............X...................... 2 2 Inst_edge_en/ebeam_sig .......X.........X...................... 2 2 msb2<9> XX...X...........X...................... 4 4 msb2<8> XX..X............X...................... 4 4 msb2<13> XX.X.............X...................... 4 4 msb1<9> XX...X...........X...................... 4 4 msb1<8> XX..X............X...................... 4 4 lsbe1<2> ......X.........XX...................... 3 3 lsbe1<1> ......X........X.X...................... 3 3 lsbe1<15> ......X.......X..X...................... 3 3 lsbe1<14> ......X......X...X...................... 3 3 lsbe1<13> ......X.....X....X...................... 3 3 lsbe1<12> ......X....X.....X...................... 3 3 lsbe1<11> ......X...X......X...................... 3 3 lsbe1<10> ......X..X.......X...................... 3 3 lsbe1<0> ......X.X........X...................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 20/34 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use lsbe2<4> 3 0 0 2 FB7_1 STD (b) (b) lsbe2<3> 3 0 0 2 FB7_2 STD (b) (b) lsbe2<2> 3 0 0 2 FB7_3 STD 45 I/O (b) lsbe2<1> 3 0 0 2 FB7_4 STD (b) (b) lsbe2<15> 3 0 0 2 FB7_5 STD 46 I/O (b) lsbe2<14> 3 0 0 2 FB7_6 STD (b) (b) lsbe2<13> 3 0 0 2 FB7_7 STD (b) (b) lsbe2<12> 3 0 0 2 FB7_8 STD (b) (b) lsbe2<11> 3 0 0 2 FB7_9 STD (b) (b) lsbe2<10> 3 0 0 2 FB7_10 STD (b) (b) lsbe2<0> 3 0 0 2 FB7_11 STD (b) (b) lsbe1<9> 3 0 0 2 FB7_12 STD 48 I/O (b) lsbe1<8> 3 0 0 2 FB7_13 STD (b) (b) lsbe1<7> 3 0 0 2 FB7_14 STD (b) (b) lsbe1<6> 3 0 0 2 FB7_15 STD 49 I/O (b) lsbe1<5> 3 0 0 2 FB7_16 STD (b) (b) lsbe1<4> 3 0 0 2 FB7_17 STD (b) (b) lsbe1<3> 3 0 0 2 FB7_18 STD (b) (b) Signals Used by Logic in Function Block 1: ebeam_oe 8: lsb1<9> 15: lsb2<15> 2: lsb1<3> 9: lsb2<0> 16: lsb2<1> 3: lsb1<4> 10: lsb2<10> 17: lsb2<2> 4: lsb1<5> 11: lsb2<11> 18: lsb2<3> 5: lsb1<6> 12: lsb2<12> 19: lsb2<4> 6: lsb1<7> 13: lsb2<13> 20: msbe2<9>/msbe2<9>_RSTF__$INT 7: lsb1<8> 14: lsb2<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsbe2<4> X.................XX.................... 3 3 lsbe2<3> X................X.X.................... 3 3 lsbe2<2> X...............X..X.................... 3 3 lsbe2<1> X..............X...X.................... 3 3 lsbe2<15> X.............X....X.................... 3 3 lsbe2<14> X............X.....X.................... 3 3 lsbe2<13> X...........X......X.................... 3 3 lsbe2<12> X..........X.......X.................... 3 3 lsbe2<11> X.........X........X.................... 3 3 lsbe2<10> X........X.........X.................... 3 3 lsbe2<0> X.......X..........X.................... 3 3 lsbe1<9> X......X...........X.................... 3 3 lsbe1<8> X.....X............X.................... 3 3 lsbe1<7> X....X.............X.................... 3 3 lsbe1<6> X...X..............X.................... 3 3 lsbe1<5> X..X...............X.................... 3 3 lsbe1<4> X.X................X.................... 3 3 lsbe1<3> XX.................X.................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 20/34 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use msbe1<6> 3 0 0 2 FB8_1 STD (b) (b) msbe1<5> 3 0 0 2 FB8_2 STD 130 I/O (b) msbe1<4> 3 0 0 2 FB8_3 STD 131 I/O (b) msbe1<3> 3 0 0 2 FB8_4 STD (b) (b) msbe1<2> 3 0 0 2 FB8_5 STD 132 I/O (b) msbe1<1> 3 0 0 2 FB8_6 STD (b) (b) msbe1<15> 3 0 0 2 FB8_7 STD (b) (b) msbe1<14> 3 0 0 2 FB8_8 STD 133 I/O (b) msbe1<13> 3 0 0 2 FB8_9 STD (b) (b) msbe1<12> 3 0 0 2 FB8_10 STD 134 I/O (b) msbe1<11> 3 0 0 2 FB8_11 STD (b) (b) msbe1<10> 3 0 0 2 FB8_12 STD (b) (b) msbe1<0> 3 0 0 2 FB8_13 STD (b) (b) lsbe2<9> 3 0 0 2 FB8_14 STD (b) (b) lsbe2<8> 3 0 0 2 FB8_15 STD (b) (b) lsbe2<7> 3 0 0 2 FB8_16 STD (b) (b) lsbe2<6> 3 0 0 2 FB8_17 STD (b) (b) lsbe2<5> 3 0 0 2 FB8_18 STD (b) (b) Signals Used by Logic in Function Block 1: ebeam_oe 8: msb1<10> 15: msb1<2> 2: lsb2<5> 9: msb1<11> 16: msb1<3> 3: lsb2<6> 10: msb1<12> 17: msb1<4> 4: lsb2<7> 11: msb1<13> 18: msb1<5> 5: lsb2<8> 12: msb1<14> 19: msb1<6> 6: lsb2<9> 13: msb1<15> 20: msbe2<9>/msbe2<9>_RSTF__$INT 7: msb1<0> 14: msb1<1> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msbe1<6> X.................XX.................... 3 3 msbe1<5> X................X.X.................... 3 3 msbe1<4> X...............X..X.................... 3 3 msbe1<3> X..............X...X.................... 3 3 msbe1<2> X.............X....X.................... 3 3 msbe1<1> X............X.....X.................... 3 3 msbe1<15> X...........X......X.................... 3 3 msbe1<14> X..........X.......X.................... 3 3 msbe1<13> X.........X........X.................... 3 3 msbe1<12> X........X.........X.................... 3 3 msbe1<11> X.......X..........X.................... 3 3 msbe1<10> X......X...........X.................... 3 3 msbe1<0> X.....X............X.................... 3 3 lsbe2<9> X....X.............X.................... 3 3 lsbe2<8> X...X..............X.................... 3 3 lsbe2<7> X..X...............X.................... 3 3 lsbe2<6> X.X................X.................... 3 3 lsbe2<5> XX.................X.................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB9 *********************************** Number of function block inputs used/remaining: 20/34 Number of signals used by logic mapping into function block: 20 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use msbe2<8> 3 0 0 2 FB9_1 STD (b) (b) msbe2<7> 3 0 0 2 FB9_2 STD 50 I/O (b) msbe2<6> 3 0 0 2 FB9_3 STD 51 I/O (b) msbe2<5> 3 0 0 2 FB9_4 STD (b) (b) msbe2<4> 3 0 0 2 FB9_5 STD 52 I/O (b) msbe2<3> 3 0 0 2 FB9_6 STD 53 I/O (b) msbe2<2> 3 0 0 2 FB9_7 STD (b) (b) msbe2<1> 3 0 0 2 FB9_8 STD 54 I/O (b) msbe2<15> 3 0 0 2 FB9_9 STD (b) (b) msbe2<14> 3 0 0 2 FB9_10 STD (b) (b) msbe2<13> 3 0 0 2 FB9_11 STD 56 I/O (b) msbe2<12> 3 0 0 2 FB9_12 STD 57 I/O (b) msbe2<11> 3 0 0 2 FB9_13 STD (b) (b) msbe2<10> 3 0 0 2 FB9_14 STD 58 I/O (b) msbe2<0> 3 0 0 2 FB9_15 STD (b) (b) msbe1<9> 3 0 0 2 FB9_16 STD (b) (b) msbe1<8> 3 0 0 2 FB9_17 STD 59 I/O (b) msbe1<7> 3 0 0 2 FB9_18 STD (b) (b) Signals Used by Logic in Function Block 1: ebeam_oe 8: msb2<12> 15: msb2<4> 2: msb1<7> 9: msb2<13> 16: msb2<5> 3: msb1<8> 10: msb2<14> 17: msb2<6> 4: msb1<9> 11: msb2<15> 18: msb2<7> 5: msb2<0> 12: msb2<1> 19: msb2<8> 6: msb2<10> 13: msb2<2> 20: msbe2<9>/msbe2<9>_RSTF__$INT 7: msb2<11> 14: msb2<3> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msbe2<8> X.................XX.................... 3 3 msbe2<7> X................X.X.................... 3 3 msbe2<6> X...............X..X.................... 3 3 msbe2<5> X..............X...X.................... 3 3 msbe2<4> X.............X....X.................... 3 3 msbe2<3> X............X.....X.................... 3 3 msbe2<2> X...........X......X.................... 3 3 msbe2<1> X..........X.......X.................... 3 3 msbe2<15> X.........X........X.................... 3 3 msbe2<14> X........X.........X.................... 3 3 msbe2<13> X.......X..........X.................... 3 3 msbe2<12> X......X...........X.................... 3 3 msbe2<11> X.....X............X.................... 3 3 msbe2<10> X....X.............X.................... 3 3 msbe2<0> X...X..............X.................... 3 3 msbe1<9> X..X...............X.................... 3 3 msbe1<8> X.X................X.................... 3 3 msbe1<7> XX.................X.................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB10 *********************************** Number of function block inputs used/remaining: 5/49 Number of signals used by logic mapping into function block: 5 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB10_1 (b) (unused) 0 0 0 5 FB10_2 117 I/O (unused) 0 0 0 5 FB10_3 118 I/O (unused) 0 0 0 5 FB10_4 (b) (unused) 0 0 0 5 FB10_5 119 I/O (unused) 0 0 0 5 FB10_6 120 I/O (unused) 0 0 0 5 FB10_7 (b) (unused) 0 0 0 5 FB10_8 121 I/O (unused) 0 0 0 5 FB10_9 (b) (unused) 0 0 0 5 FB10_10 124 I/O (unused) 0 0 0 5 FB10_11 125 I/O (unused) 0 0 0 5 FB10_12 126 I/O (unused) 0 0 0 5 FB10_13 (b) (unused) 0 0 0 5 FB10_14 128 I/O (unused) 0 0 0 5 FB10_15 (b) (unused) 0 0 0 5 FB10_16 (b) msbe2<9>/msbe2<9>_RSTF__$INT 1 0 0 4 FB10_17 STD 129 I/O (b) msbe2<9> 3 0 0 2 FB10_18 STD (b) (b) Signals Used by Logic in Function Block 1: ebeam_oe 3: msbe2<9>/msbe2<9>_RSTF__$INT 5: reset_timer 2: msb2<9> 4: reset Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msbe2<9>/msbe2<9>_RSTF__$INT ...XX................................... 2 2 msbe2<9> XXX..................................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB11 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB11_1 (b) (unused) 0 0 0 5 FB11_2 (b) (unused) 0 0 0 5 FB11_3 60 I/O (unused) 0 0 0 5 FB11_4 (b) (unused) 0 0 0 5 FB11_5 61 I/O (unused) 0 0 0 5 FB11_6 (b) (unused) 0 0 0 5 FB11_7 (b) (unused) 0 0 0 5 FB11_8 (b) (unused) 0 0 0 5 FB11_9 (b) (unused) 0 0 0 5 FB11_10 64 I/O (unused) 0 0 0 5 FB11_11 66 I/O (unused) 0 0 0 5 FB11_12 68 I/O (unused) 0 0 0 5 FB11_13 (b) (unused) 0 0 0 5 FB11_14 69 I/O (unused) 0 0 0 5 FB11_15 (b) (unused) 0 0 0 5 FB11_16 (b) (unused) 0 0 0 5 FB11_17 70 I/O (unused) 0 0 0 5 FB11_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB12 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB12_1 (b) (unused) 0 0 0 5 FB12_2 110 I/O (unused) 0 0 0 5 FB12_3 111 I/O (unused) 0 0 0 5 FB12_4 (b) (unused) 0 0 0 5 FB12_5 112 I/O (unused) 0 0 0 5 FB12_6 (b) (unused) 0 0 0 5 FB12_7 (b) (unused) 0 0 0 5 FB12_8 113 I/O (unused) 0 0 0 5 FB12_9 (b) (unused) 0 0 0 5 FB12_10 115 I/O (unused) 0 0 0 5 FB12_11 (b) (unused) 0 0 0 5 FB12_12 116 I/O (unused) 0 0 0 5 FB12_13 (b) (unused) 0 0 0 5 FB12_14 (b) (unused) 0 0 0 5 FB12_15 (b) (unused) 0 0 0 5 FB12_16 (b) (unused) 0 0 0 5 FB12_17 (b) (unused) 0 0 0 5 FB12_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB13 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB13_1 (b) (unused) 0 0 0 5 FB13_2 71 I/O (unused) 0 0 0 5 FB13_3 (b) (unused) 0 0 0 5 FB13_4 (b) (unused) 0 0 0 5 FB13_5 (b) (unused) 0 0 0 5 FB13_6 (b) (unused) 0 0 0 5 FB13_7 (b) (unused) 0 0 0 5 FB13_8 74 I/O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) (unused) 0 0 0 5 FB13_11 75 I/O (unused) 0 0 0 5 FB13_12 (b) (unused) 0 0 0 5 FB13_13 (b) (unused) 0 0 0 5 FB13_14 76 I/O (unused) 0 0 0 5 FB13_15 77 I/O (unused) 0 0 0 5 FB13_16 (b) (unused) 0 0 0 5 FB13_17 78 I/O I (unused) 0 0 0 5 FB13_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB14 *********************************** Number of function block inputs used/remaining: 36/18 Number of signals used by logic mapping into function block: 36 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB14_1 (b) (unused) 0 0 0 5 FB14_2 (b) ebeam_data<7> 4 0 0 1 FB14_3 STD 100 I/O O (unused) 0 0 0 5 FB14_4 (b) ebeam_data<6> 4 0 0 1 FB14_5 STD 101 I/O O ebeam_data<5> 4 0 0 1 FB14_6 STD 102 I/O O (unused) 0 0 0 5 FB14_7 (b) ebeam_data<4> 4 0 0 1 FB14_8 STD 103 I/O O (unused) 0 0 0 5 FB14_9 (b) ebeam_data<3> 4 0 0 1 FB14_10 STD 104 I/O O ebeam_data<2> 4 0 0 1 FB14_11 STD 105 I/O O (unused) 0 0 0 5 FB14_12 (b) (unused) 0 0 0 5 FB14_13 (b) ebeam_data<1> 4 0 0 1 FB14_14 STD 106 I/O O ebeam_data<0> 4 0 0 1 FB14_15 STD 107 I/O O (unused) 0 0 0 5 FB14_16 (b) (unused) 0 0 0 5 FB14_17 (b) (unused) 0 0 0 5 FB14_18 (b) Signals Used by Logic in Function Block 1: loword 13: lsbe2<3> 25: msbe1<7> 2: lsbe1<0> 14: lsbe2<4> 26: msbe2<0> 3: lsbe1<1> 15: lsbe2<5> 27: msbe2<1> 4: lsbe1<2> 16: lsbe2<6> 28: msbe2<2> 5: lsbe1<3> 17: lsbe2<7> 29: msbe2<3> 6: lsbe1<4> 18: msbe1<0> 30: msbe2<4> 7: lsbe1<5> 19: msbe1<1> 31: msbe2<5> 8: lsbe1<6> 20: msbe1<2> 32: msbe2<6> 9: lsbe1<7> 21: msbe1<3> 33: msbe2<7> 10: lsbe2<0> 22: msbe1<4> 34: timer1 11: lsbe2<1> 23: msbe1<5> 35: timer2 12: lsbe2<2> 24: msbe1<6> 36: upword Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ebeam_data<7> X.......X.......X.......X.......XXXX.... 8 8 ebeam_data<6> X......X.......X.......X.......X.XXX.... 8 8 ebeam_data<5> X.....X.......X.......X.......X..XXX.... 8 8 ebeam_data<4> X....X.......X.......X.......X...XXX.... 8 8 ebeam_data<3> X...X.......X.......X.......X....XXX.... 8 8 ebeam_data<2> X..X.......X.......X.......X.....XXX.... 8 8 ebeam_data<1> X.X.......X.......X.......X......XXX.... 8 8 ebeam_data<0> XX.......X.......X.......X.......XXX.... 8 8 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB15 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB15_1 (b) (unused) 0 0 0 5 FB15_2 79 I/O I (unused) 0 0 0 5 FB15_3 80 I/O I (unused) 0 0 0 5 FB15_4 (b) (unused) 0 0 0 5 FB15_5 (b) (unused) 0 0 0 5 FB15_6 (b) (unused) 0 0 0 5 FB15_7 (b) (unused) 0 0 0 5 FB15_8 81 I/O I (unused) 0 0 0 5 FB15_9 (b) (unused) 0 0 0 5 FB15_10 82 I/O I (unused) 0 0 0 5 FB15_11 83 I/O (unused) 0 0 0 5 FB15_12 85 I/O (unused) 0 0 0 5 FB15_13 (b) (unused) 0 0 0 5 FB15_14 86 I/O (unused) 0 0 0 5 FB15_15 87 I/O (unused) 0 0 0 5 FB15_16 (b) (unused) 0 0 0 5 FB15_17 88 I/O (unused) 0 0 0 5 FB15_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB16 *********************************** Number of function block inputs used/remaining: 36/18 Number of signals used by logic mapping into function block: 36 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB16_1 (b) ebeam_data<15> 4 0 0 1 FB16_2 STD 91 I/O O ebeam_data<14> 4 0 0 1 FB16_3 STD 92 I/O O (unused) 0 0 0 5 FB16_4 (b) ebeam_data<13> 4 0 0 1 FB16_5 STD 93 I/O O ebeam_data<12> 4 0 0 1 FB16_6 STD 94 I/O O (unused) 0 0 0 5 FB16_7 (b) ebeam_data<11> 4 0 0 1 FB16_8 STD 95 I/O O (unused) 0 0 0 5 FB16_9 (b) ebeam_data<10> 4 0 0 1 FB16_10 STD 96 I/O O ebeam_data<9> 4 0 0 1 FB16_11 STD 97 I/O O ebeam_data<8> 4 0 0 1 FB16_12 STD 98 I/O O (unused) 0 0 0 5 FB16_13 (b) (unused) 0 0 0 5 FB16_14 (b) (unused) 0 0 0 5 FB16_15 (b) (unused) 0 0 0 5 FB16_16 (b) (unused) 0 0 0 5 FB16_17 (b) (unused) 0 0 0 5 FB16_18 (b) Signals Used by Logic in Function Block 1: loword 13: lsbe2<13> 25: msbe1<9> 2: lsbe1<10> 14: lsbe2<14> 26: msbe2<10> 3: lsbe1<11> 15: lsbe2<15> 27: msbe2<11> 4: lsbe1<12> 16: lsbe2<8> 28: msbe2<12> 5: lsbe1<13> 17: lsbe2<9> 29: msbe2<13> 6: lsbe1<14> 18: msbe1<10> 30: msbe2<14> 7: lsbe1<15> 19: msbe1<11> 31: msbe2<15> 8: lsbe1<8> 20: msbe1<12> 32: msbe2<8> 9: lsbe1<9> 21: msbe1<13> 33: msbe2<9> 10: lsbe2<10> 22: msbe1<14> 34: timer1 11: lsbe2<11> 23: msbe1<15> 35: timer2 12: lsbe2<12> 24: msbe1<8> 36: upword Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ebeam_data<15> X.....X.......X.......X.......X..XXX.... 8 8 ebeam_data<14> X....X.......X.......X.......X...XXX.... 8 8 ebeam_data<13> X...X.......X.......X.......X....XXX.... 8 8 ebeam_data<12> X..X.......X.......X.......X.....XXX.... 8 8 ebeam_data<11> X.X.......X.......X.......X......XXX.... 8 8 ebeam_data<10> XX.......X.......X.......X.......XXX.... 8 8 ebeam_data<9> X.......X.......X.......X.......XXXX.... 8 8 ebeam_data<8> X......X.......X.......X.......X.XXX.... 8 8 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. Inst_edge_en/ebeam_sig.D = ebeam_sig; Inst_edge_en/ebeam_sig.CLK = timeclk; // GCK Inst_edge_en/ebeam_sig.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; Inst_edge_en/state_FFT1.T = Inst_edge_en/state_FFT2; Inst_edge_en/state_FFT1.CLK = timeclk; // GCK Inst_edge_en/state_FFT1.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; !Inst_edge_en/state_FFT2.T = Inst_edge_en/state_FFT1 & !Inst_edge_en/state_FFT2 & Inst_edge_en/ebeam_sig # !Inst_edge_en/state_FFT1 & !Inst_edge_en/state_FFT2 & !Inst_edge_en/ebeam_sig; Inst_edge_en/state_FFT2.CLK = timeclk; // GCK Inst_edge_en/state_FFT2.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<0>.T = Vcc; cnt_lsb<0>.CLK = timeclk; // GCK cnt_lsb<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<10>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<10>.CLK = timeclk; // GCK cnt_lsb<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<11>.T = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<11>.CLK = timeclk; // GCK cnt_lsb<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<12>.T = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<12>.CLK = timeclk; // GCK cnt_lsb<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<13>.T = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<13>.CLK = timeclk; // GCK cnt_lsb<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<14>.T = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<14>.CLK = timeclk; // GCK cnt_lsb<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<15>.T = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9>; cnt_lsb<15>.CLK = timeclk; // GCK cnt_lsb<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<1>.T = cnt_lsb<0>; cnt_lsb<1>.CLK = timeclk; // GCK cnt_lsb<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<2>.T = cnt_lsb<0> & cnt_lsb<1>; cnt_lsb<2>.CLK = timeclk; // GCK cnt_lsb<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<3>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2>; cnt_lsb<3>.CLK = timeclk; // GCK cnt_lsb<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<4>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3>; cnt_lsb<4>.CLK = timeclk; // GCK cnt_lsb<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<5>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4>; cnt_lsb<5>.CLK = timeclk; // GCK cnt_lsb<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<6>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5>; cnt_lsb<6>.CLK = timeclk; // GCK cnt_lsb<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<7>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6>; cnt_lsb<7>.CLK = timeclk; // GCK cnt_lsb<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<8>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7>; cnt_lsb<8>.CLK = timeclk; // GCK cnt_lsb<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_lsb<9>.T = cnt_lsb<0> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8>; cnt_lsb<9>.CLK = timeclk; // GCK cnt_lsb<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<0>.T = Vcc; cnt_msb<0>.CLK = timeclk; // GCK cnt_msb<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<0>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<10>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<10>.CLK = timeclk; // GCK cnt_msb<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<10>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<11>.T = cnt_msb<0> & cnt_msb<10> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<11>.CLK = timeclk; // GCK cnt_msb<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<11>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<12>.T = cnt_msb<0> & cnt_msb<10> & cnt_msb<11> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<12>.CLK = timeclk; // GCK cnt_msb<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<12>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<13>.T = cnt_msb<0> & cnt_msb<10> & cnt_msb<11> & cnt_msb<12> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<13>.CLK = timeclk; // GCK cnt_msb<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<13>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<14>.T = cnt_msb<0> & cnt_msb<10> & cnt_msb<11> & cnt_msb<12> & cnt_msb<13> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<14>.CLK = timeclk; // GCK cnt_msb<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<14>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<15>.T = cnt_msb<0> & cnt_msb<10> & cnt_msb<11> & cnt_msb<12> & cnt_msb<13> & cnt_msb<14> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8> & cnt_msb<9>; cnt_msb<15>.CLK = timeclk; // GCK cnt_msb<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<15>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<1>.T = cnt_msb<0>; cnt_msb<1>.CLK = timeclk; // GCK cnt_msb<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<1>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<2>.T = cnt_msb<0> & cnt_msb<1>; cnt_msb<2>.CLK = timeclk; // GCK cnt_msb<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<2>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<3>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2>; cnt_msb<3>.CLK = timeclk; // GCK cnt_msb<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<3>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<4>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3>; cnt_msb<4>.CLK = timeclk; // GCK cnt_msb<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<4>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<5>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4>; cnt_msb<5>.CLK = timeclk; // GCK cnt_msb<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<5>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<6>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5>; cnt_msb<6>.CLK = timeclk; // GCK cnt_msb<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<6>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<7>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6>; cnt_msb<7>.CLK = timeclk; // GCK cnt_msb<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<7>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<8>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7>; cnt_msb<8>.CLK = timeclk; // GCK cnt_msb<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<8>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; cnt_msb<9>.T = cnt_msb<0> & cnt_msb<1> & cnt_msb<2> & cnt_msb<3> & cnt_msb<4> & cnt_msb<5> & cnt_msb<6> & cnt_msb<7> & cnt_msb<8>; cnt_msb<9>.CLK = timeclk; // GCK cnt_msb<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; cnt_msb<9>.CE = cnt_lsb<0> & cnt_lsb<10> & cnt_lsb<11> & cnt_lsb<12> & cnt_lsb<13> & cnt_lsb<14> & cnt_lsb<1> & cnt_lsb<2> & cnt_lsb<3> & cnt_lsb<4> & cnt_lsb<5> & cnt_lsb<6> & cnt_lsb<7> & cnt_lsb<8> & cnt_lsb<9> & cnt_lsb<15>; ebeam_data<0> = msbe1<0> & !timer1 & !upword # lsbe1<0> & !timer1 & upword & !loword # msbe2<0> & timer1 & !timer2 & !upword # lsbe2<0> & timer1 & !timer2 & upword & !loword; ebeam_data<10> = msbe1<10> & !timer1 & !upword # lsbe1<10> & !timer1 & upword & !loword # msbe2<10> & timer1 & !timer2 & !upword # lsbe2<10> & timer1 & !timer2 & upword & !loword; ebeam_data<11> = msbe1<11> & !timer1 & !upword # lsbe1<11> & !timer1 & upword & !loword # msbe2<11> & timer1 & !timer2 & !upword # lsbe2<11> & timer1 & !timer2 & upword & !loword; ebeam_data<12> = msbe1<12> & !timer1 & !upword # lsbe1<12> & !timer1 & upword & !loword # msbe2<12> & timer1 & !timer2 & !upword # lsbe2<12> & timer1 & !timer2 & upword & !loword; ebeam_data<13> = msbe1<13> & !timer1 & !upword # lsbe1<13> & !timer1 & upword & !loword # msbe2<13> & timer1 & !timer2 & !upword # lsbe2<13> & timer1 & !timer2 & upword & !loword; ebeam_data<14> = msbe1<14> & !timer1 & !upword # lsbe1<14> & !timer1 & upword & !loword # msbe2<14> & timer1 & !timer2 & !upword # lsbe2<14> & timer1 & !timer2 & upword & !loword; ebeam_data<15> = msbe1<15> & !timer1 & !upword # lsbe1<15> & !timer1 & upword & !loword # msbe2<15> & timer1 & !timer2 & !upword # lsbe2<15> & timer1 & !timer2 & upword & !loword; ebeam_data<1> = msbe1<1> & !timer1 & !upword # lsbe1<1> & !timer1 & upword & !loword # msbe2<1> & timer1 & !timer2 & !upword # lsbe2<1> & timer1 & !timer2 & upword & !loword; ebeam_data<2> = msbe1<2> & !timer1 & !upword # lsbe1<2> & !timer1 & upword & !loword # msbe2<2> & timer1 & !timer2 & !upword # lsbe2<2> & timer1 & !timer2 & upword & !loword; ebeam_data<3> = msbe1<3> & !timer1 & !upword # lsbe1<3> & !timer1 & upword & !loword # msbe2<3> & timer1 & !timer2 & !upword # lsbe2<3> & timer1 & !timer2 & upword & !loword; ebeam_data<4> = msbe1<4> & !timer1 & !upword # lsbe1<4> & !timer1 & upword & !loword # msbe2<4> & timer1 & !timer2 & !upword # lsbe2<4> & timer1 & !timer2 & upword & !loword; ebeam_data<5> = msbe1<5> & !timer1 & !upword # lsbe1<5> & !timer1 & upword & !loword # msbe2<5> & timer1 & !timer2 & !upword # lsbe2<5> & timer1 & !timer2 & upword & !loword; ebeam_data<6> = msbe1<6> & !timer1 & !upword # lsbe1<6> & !timer1 & upword & !loword # msbe2<6> & timer1 & !timer2 & !upword # lsbe2<6> & timer1 & !timer2 & upword & !loword; ebeam_data<7> = msbe1<7> & !timer1 & !upword # lsbe1<7> & !timer1 & upword & !loword # msbe2<7> & timer1 & !timer2 & !upword # lsbe2<7> & timer1 & !timer2 & upword & !loword; ebeam_data<8> = msbe1<8> & !timer1 & !upword # lsbe1<8> & !timer1 & upword & !loword # msbe2<8> & timer1 & !timer2 & !upword # lsbe2<8> & timer1 & !timer2 & upword & !loword; ebeam_data<9> = msbe1<9> & !timer1 & !upword # lsbe1<9> & !timer1 & upword & !loword # msbe2<9> & timer1 & !timer2 & !upword # lsbe2<9> & timer1 & !timer2 & upword & !loword; lsb1<0>.D = cnt_lsb<0>; lsb1<0>.CLK = timeclk; // GCK lsb1<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<0>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<10>.D = cnt_lsb<10>; lsb1<10>.CLK = timeclk; // GCK lsb1<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<10>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<11>.D = cnt_lsb<11>; lsb1<11>.CLK = timeclk; // GCK lsb1<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<11>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<12>.D = cnt_lsb<12>; lsb1<12>.CLK = timeclk; // GCK lsb1<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<12>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<13>.D = cnt_lsb<13>; lsb1<13>.CLK = timeclk; // GCK lsb1<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<13>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<14>.D = cnt_lsb<14>; lsb1<14>.CLK = timeclk; // GCK lsb1<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<14>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<15>.D = cnt_lsb<15>; lsb1<15>.CLK = timeclk; // GCK lsb1<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<15>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<1>.D = cnt_lsb<1>; lsb1<1>.CLK = timeclk; // GCK lsb1<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<1>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<2>.D = cnt_lsb<2>; lsb1<2>.CLK = timeclk; // GCK lsb1<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<2>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<3>.D = cnt_lsb<3>; lsb1<3>.CLK = timeclk; // GCK lsb1<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<3>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<4>.D = cnt_lsb<4>; lsb1<4>.CLK = timeclk; // GCK lsb1<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<4>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<5>.D = cnt_lsb<5>; lsb1<5>.CLK = timeclk; // GCK lsb1<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<5>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<6>.D = cnt_lsb<6>; lsb1<6>.CLK = timeclk; // GCK lsb1<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<6>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<7>.D = cnt_lsb<7>; lsb1<7>.CLK = timeclk; // GCK lsb1<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<7>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<8>.D = cnt_lsb<8>; lsb1<8>.CLK = timeclk; // GCK lsb1<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<8>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb1<9>.D = cnt_lsb<9>; lsb1<9>.CLK = timeclk; // GCK lsb1<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb1<9>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<0>.D = cnt_lsb<0>; lsb2<0>.CLK = timeclk; // GCK lsb2<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<0>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<10>.D = cnt_lsb<10>; lsb2<10>.CLK = timeclk; // GCK lsb2<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<10>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<11>.D = cnt_lsb<11>; lsb2<11>.CLK = timeclk; // GCK lsb2<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<11>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<12>.D = cnt_lsb<12>; lsb2<12>.CLK = timeclk; // GCK lsb2<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<12>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<13>.D = cnt_lsb<13>; lsb2<13>.CLK = timeclk; // GCK lsb2<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<13>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<14>.D = cnt_lsb<14>; lsb2<14>.CLK = timeclk; // GCK lsb2<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<14>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<15>.D = cnt_lsb<15>; lsb2<15>.CLK = timeclk; // GCK lsb2<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<15>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<1>.D = cnt_lsb<1>; lsb2<1>.CLK = timeclk; // GCK lsb2<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<1>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<2>.D = cnt_lsb<2>; lsb2<2>.CLK = timeclk; // GCK lsb2<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<2>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<3>.D = cnt_lsb<3>; lsb2<3>.CLK = timeclk; // GCK lsb2<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<3>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<4>.D = cnt_lsb<4>; lsb2<4>.CLK = timeclk; // GCK lsb2<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<4>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<5>.D = cnt_lsb<5>; lsb2<5>.CLK = timeclk; // GCK lsb2<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<5>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<6>.D = cnt_lsb<6>; lsb2<6>.CLK = timeclk; // GCK lsb2<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<6>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<7>.D = cnt_lsb<7>; lsb2<7>.CLK = timeclk; // GCK lsb2<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<7>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<8>.D = cnt_lsb<8>; lsb2<8>.CLK = timeclk; // GCK lsb2<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<8>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsb2<9>.D = cnt_lsb<9>; lsb2<9>.CLK = timeclk; // GCK lsb2<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsb2<9>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; lsbe1<0>.D = lsb1<0>; lsbe1<0>.CLK = sysclk; // GCK lsbe1<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<0>.CE = ebeam_oe; lsbe1<10>.D = lsb1<10>; lsbe1<10>.CLK = sysclk; // GCK lsbe1<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<10>.CE = ebeam_oe; lsbe1<11>.D = lsb1<11>; lsbe1<11>.CLK = sysclk; // GCK lsbe1<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<11>.CE = ebeam_oe; lsbe1<12>.D = lsb1<12>; lsbe1<12>.CLK = sysclk; // GCK lsbe1<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<12>.CE = ebeam_oe; lsbe1<13>.D = lsb1<13>; lsbe1<13>.CLK = sysclk; // GCK lsbe1<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<13>.CE = ebeam_oe; lsbe1<14>.D = lsb1<14>; lsbe1<14>.CLK = sysclk; // GCK lsbe1<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<14>.CE = ebeam_oe; lsbe1<15>.D = lsb1<15>; lsbe1<15>.CLK = sysclk; // GCK lsbe1<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<15>.CE = ebeam_oe; lsbe1<1>.D = lsb1<1>; lsbe1<1>.CLK = sysclk; // GCK lsbe1<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<1>.CE = ebeam_oe; lsbe1<2>.D = lsb1<2>; lsbe1<2>.CLK = sysclk; // GCK lsbe1<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<2>.CE = ebeam_oe; lsbe1<3>.D = lsb1<3>; lsbe1<3>.CLK = sysclk; // GCK lsbe1<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<3>.CE = ebeam_oe; lsbe1<4>.D = lsb1<4>; lsbe1<4>.CLK = sysclk; // GCK lsbe1<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<4>.CE = ebeam_oe; lsbe1<5>.D = lsb1<5>; lsbe1<5>.CLK = sysclk; // GCK lsbe1<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<5>.CE = ebeam_oe; lsbe1<6>.D = lsb1<6>; lsbe1<6>.CLK = sysclk; // GCK lsbe1<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<6>.CE = ebeam_oe; lsbe1<7>.D = lsb1<7>; lsbe1<7>.CLK = sysclk; // GCK lsbe1<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<7>.CE = ebeam_oe; lsbe1<8>.D = lsb1<8>; lsbe1<8>.CLK = sysclk; // GCK lsbe1<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<8>.CE = ebeam_oe; lsbe1<9>.D = lsb1<9>; lsbe1<9>.CLK = sysclk; // GCK lsbe1<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe1<9>.CE = ebeam_oe; lsbe2<0>.D = lsb2<0>; lsbe2<0>.CLK = sysclk; // GCK lsbe2<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<0>.CE = ebeam_oe; lsbe2<10>.D = lsb2<10>; lsbe2<10>.CLK = sysclk; // GCK lsbe2<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<10>.CE = ebeam_oe; lsbe2<11>.D = lsb2<11>; lsbe2<11>.CLK = sysclk; // GCK lsbe2<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<11>.CE = ebeam_oe; lsbe2<12>.D = lsb2<12>; lsbe2<12>.CLK = sysclk; // GCK lsbe2<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<12>.CE = ebeam_oe; lsbe2<13>.D = lsb2<13>; lsbe2<13>.CLK = sysclk; // GCK lsbe2<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<13>.CE = ebeam_oe; lsbe2<14>.D = lsb2<14>; lsbe2<14>.CLK = sysclk; // GCK lsbe2<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<14>.CE = ebeam_oe; lsbe2<15>.D = lsb2<15>; lsbe2<15>.CLK = sysclk; // GCK lsbe2<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<15>.CE = ebeam_oe; lsbe2<1>.D = lsb2<1>; lsbe2<1>.CLK = sysclk; // GCK lsbe2<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<1>.CE = ebeam_oe; lsbe2<2>.D = lsb2<2>; lsbe2<2>.CLK = sysclk; // GCK lsbe2<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<2>.CE = ebeam_oe; lsbe2<3>.D = lsb2<3>; lsbe2<3>.CLK = sysclk; // GCK lsbe2<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<3>.CE = ebeam_oe; lsbe2<4>.D = lsb2<4>; lsbe2<4>.CLK = sysclk; // GCK lsbe2<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<4>.CE = ebeam_oe; lsbe2<5>.D = lsb2<5>; lsbe2<5>.CLK = sysclk; // GCK lsbe2<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<5>.CE = ebeam_oe; lsbe2<6>.D = lsb2<6>; lsbe2<6>.CLK = sysclk; // GCK lsbe2<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<6>.CE = ebeam_oe; lsbe2<7>.D = lsb2<7>; lsbe2<7>.CLK = sysclk; // GCK lsbe2<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<7>.CE = ebeam_oe; lsbe2<8>.D = lsb2<8>; lsbe2<8>.CLK = sysclk; // GCK lsbe2<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<8>.CE = ebeam_oe; lsbe2<9>.D = lsb2<9>; lsbe2<9>.CLK = sysclk; // GCK lsbe2<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; lsbe2<9>.CE = ebeam_oe; msb1<0>.D = cnt_msb<0>; msb1<0>.CLK = timeclk; // GCK msb1<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<0>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<10>.D = cnt_msb<10>; msb1<10>.CLK = timeclk; // GCK msb1<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<10>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<11>.D = cnt_msb<11>; msb1<11>.CLK = timeclk; // GCK msb1<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<11>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<12>.D = cnt_msb<12>; msb1<12>.CLK = timeclk; // GCK msb1<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<12>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<13>.D = cnt_msb<13>; msb1<13>.CLK = timeclk; // GCK msb1<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<13>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<14>.D = cnt_msb<14>; msb1<14>.CLK = timeclk; // GCK msb1<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<14>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<15>.D = cnt_msb<15>; msb1<15>.CLK = timeclk; // GCK msb1<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<15>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<1>.D = cnt_msb<1>; msb1<1>.CLK = timeclk; // GCK msb1<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<1>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<2>.D = cnt_msb<2>; msb1<2>.CLK = timeclk; // GCK msb1<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<2>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<3>.D = cnt_msb<3>; msb1<3>.CLK = timeclk; // GCK msb1<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<3>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<4>.D = cnt_msb<4>; msb1<4>.CLK = timeclk; // GCK msb1<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<4>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<5>.D = cnt_msb<5>; msb1<5>.CLK = timeclk; // GCK msb1<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<5>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<6>.D = cnt_msb<6>; msb1<6>.CLK = timeclk; // GCK msb1<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<6>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<7>.D = cnt_msb<7>; msb1<7>.CLK = timeclk; // GCK msb1<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<7>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<8>.D = cnt_msb<8>; msb1<8>.CLK = timeclk; // GCK msb1<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<8>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb1<9>.D = cnt_msb<9>; msb1<9>.CLK = timeclk; // GCK msb1<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb1<9>.CE = !Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<0>.D = cnt_msb<0>; msb2<0>.CLK = timeclk; // GCK msb2<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<0>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<10>.D = cnt_msb<10>; msb2<10>.CLK = timeclk; // GCK msb2<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<10>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<11>.D = cnt_msb<11>; msb2<11>.CLK = timeclk; // GCK msb2<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<11>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<12>.D = cnt_msb<12>; msb2<12>.CLK = timeclk; // GCK msb2<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<12>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<13>.D = cnt_msb<13>; msb2<13>.CLK = timeclk; // GCK msb2<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<13>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<14>.D = cnt_msb<14>; msb2<14>.CLK = timeclk; // GCK msb2<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<14>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<15>.D = cnt_msb<15>; msb2<15>.CLK = timeclk; // GCK msb2<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<15>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<1>.D = cnt_msb<1>; msb2<1>.CLK = timeclk; // GCK msb2<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<1>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<2>.D = cnt_msb<2>; msb2<2>.CLK = timeclk; // GCK msb2<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<2>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<3>.D = cnt_msb<3>; msb2<3>.CLK = timeclk; // GCK msb2<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<3>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<4>.D = cnt_msb<4>; msb2<4>.CLK = timeclk; // GCK msb2<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<4>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<5>.D = cnt_msb<5>; msb2<5>.CLK = timeclk; // GCK msb2<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<5>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<6>.D = cnt_msb<6>; msb2<6>.CLK = timeclk; // GCK msb2<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<6>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<7>.D = cnt_msb<7>; msb2<7>.CLK = timeclk; // GCK msb2<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<7>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<8>.D = cnt_msb<8>; msb2<8>.CLK = timeclk; // GCK msb2<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<8>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msb2<9>.D = cnt_msb<9>; msb2<9>.CLK = timeclk; // GCK msb2<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msb2<9>.CE = Inst_edge_en/state_FFT1 & Inst_edge_en/state_FFT2; msbe1<0>.D = msb1<0>; msbe1<0>.CLK = sysclk; // GCK msbe1<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<0>.CE = ebeam_oe; msbe1<10>.D = msb1<10>; msbe1<10>.CLK = sysclk; // GCK msbe1<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<10>.CE = ebeam_oe; msbe1<11>.D = msb1<11>; msbe1<11>.CLK = sysclk; // GCK msbe1<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<11>.CE = ebeam_oe; msbe1<12>.D = msb1<12>; msbe1<12>.CLK = sysclk; // GCK msbe1<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<12>.CE = ebeam_oe; msbe1<13>.D = msb1<13>; msbe1<13>.CLK = sysclk; // GCK msbe1<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<13>.CE = ebeam_oe; msbe1<14>.D = msb1<14>; msbe1<14>.CLK = sysclk; // GCK msbe1<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<14>.CE = ebeam_oe; msbe1<15>.D = msb1<15>; msbe1<15>.CLK = sysclk; // GCK msbe1<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<15>.CE = ebeam_oe; msbe1<1>.D = msb1<1>; msbe1<1>.CLK = sysclk; // GCK msbe1<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<1>.CE = ebeam_oe; msbe1<2>.D = msb1<2>; msbe1<2>.CLK = sysclk; // GCK msbe1<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<2>.CE = ebeam_oe; msbe1<3>.D = msb1<3>; msbe1<3>.CLK = sysclk; // GCK msbe1<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<3>.CE = ebeam_oe; msbe1<4>.D = msb1<4>; msbe1<4>.CLK = sysclk; // GCK msbe1<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<4>.CE = ebeam_oe; msbe1<5>.D = msb1<5>; msbe1<5>.CLK = sysclk; // GCK msbe1<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<5>.CE = ebeam_oe; msbe1<6>.D = msb1<6>; msbe1<6>.CLK = sysclk; // GCK msbe1<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<6>.CE = ebeam_oe; msbe1<7>.D = msb1<7>; msbe1<7>.CLK = sysclk; // GCK msbe1<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<7>.CE = ebeam_oe; msbe1<8>.D = msb1<8>; msbe1<8>.CLK = sysclk; // GCK msbe1<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<8>.CE = ebeam_oe; msbe1<9>.D = msb1<9>; msbe1<9>.CLK = sysclk; // GCK msbe1<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe1<9>.CE = ebeam_oe; msbe2<0>.D = msb2<0>; msbe2<0>.CLK = sysclk; // GCK msbe2<0>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<0>.CE = ebeam_oe; msbe2<10>.D = msb2<10>; msbe2<10>.CLK = sysclk; // GCK msbe2<10>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<10>.CE = ebeam_oe; msbe2<11>.D = msb2<11>; msbe2<11>.CLK = sysclk; // GCK msbe2<11>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<11>.CE = ebeam_oe; msbe2<12>.D = msb2<12>; msbe2<12>.CLK = sysclk; // GCK msbe2<12>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<12>.CE = ebeam_oe; msbe2<13>.D = msb2<13>; msbe2<13>.CLK = sysclk; // GCK msbe2<13>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<13>.CE = ebeam_oe; msbe2<14>.D = msb2<14>; msbe2<14>.CLK = sysclk; // GCK msbe2<14>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<14>.CE = ebeam_oe; msbe2<15>.D = msb2<15>; msbe2<15>.CLK = sysclk; // GCK msbe2<15>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<15>.CE = ebeam_oe; msbe2<1>.D = msb2<1>; msbe2<1>.CLK = sysclk; // GCK msbe2<1>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<1>.CE = ebeam_oe; msbe2<2>.D = msb2<2>; msbe2<2>.CLK = sysclk; // GCK msbe2<2>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<2>.CE = ebeam_oe; msbe2<3>.D = msb2<3>; msbe2<3>.CLK = sysclk; // GCK msbe2<3>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<3>.CE = ebeam_oe; msbe2<4>.D = msb2<4>; msbe2<4>.CLK = sysclk; // GCK msbe2<4>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<4>.CE = ebeam_oe; msbe2<5>.D = msb2<5>; msbe2<5>.CLK = sysclk; // GCK msbe2<5>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<5>.CE = ebeam_oe; msbe2<6>.D = msb2<6>; msbe2<6>.CLK = sysclk; // GCK msbe2<6>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<6>.CE = ebeam_oe; msbe2<7>.D = msb2<7>; msbe2<7>.CLK = sysclk; // GCK msbe2<7>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<7>.CE = ebeam_oe; msbe2<8>.D = msb2<8>; msbe2<8>.CLK = sysclk; // GCK msbe2<8>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<8>.CE = ebeam_oe; msbe2<9>.D = msb2<9>; msbe2<9>.CLK = sysclk; // GCK msbe2<9>.AR = !msbe2<9>/msbe2<9>_RSTF__$INT; msbe2<9>.CE = ebeam_oe; msbe2<9>/msbe2<9>_RSTF__$INT = reset_timer & reset; Legend: .COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC95288XL-7-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 TIE 74 TIE 3 TIE 75 TIE 4 TIE 76 TIE 5 TIE 77 TIE 6 TIE 78 ebeam_oe 7 TIE 79 timer1 8 VCC 80 timer2 9 TIE 81 upword 10 TIE 82 loword 11 TIE 83 TIE 12 TIE 84 VCC 13 TIE 85 TIE 14 TIE 86 TIE 15 TIE 87 TIE 16 TIE 88 TIE 17 TIE 89 GND 18 GND 90 GND 19 TIE 91 ebeam_data<15> 20 TIE 92 ebeam_data<14> 21 TIE 93 ebeam_data<13> 22 TIE 94 ebeam_data<12> 23 TIE 95 ebeam_data<11> 24 TIE 96 ebeam_data<10> 25 TIE 97 ebeam_data<9> 26 TIE 98 ebeam_data<8> 27 TIE 99 GND 28 TIE 100 ebeam_data<7> 29 GND 101 ebeam_data<6> 30 timeclk 102 ebeam_data<5> 31 TIE 103 ebeam_data<4> 32 sysclk 104 ebeam_data<3> 33 TIE 105 ebeam_data<2> 34 TIE 106 ebeam_data<1> 35 TIE 107 ebeam_data<0> 36 GND 108 GND 37 VCC 109 VCC 38 TIE 110 TIE 39 TIE 111 TIE 40 ebeam_sig 112 TIE 41 TIE 113 TIE 42 VCC 114 GND 43 TIE 115 TIE 44 TIE 116 TIE 45 TIE 117 TIE 46 TIE 118 TIE 47 GND 119 TIE 48 TIE 120 TIE 49 TIE 121 TIE 50 TIE 122 TDO 51 TIE 123 GND 52 TIE 124 TIE 53 TIE 125 TIE 54 TIE 126 TIE 55 VCC 127 VCC 56 TIE 128 TIE 57 TIE 129 TIE 58 TIE 130 TIE 59 TIE 131 TIE 60 TIE 132 TIE 61 TIE 133 TIE 62 GND 134 TIE 63 TDI 135 TIE 64 TIE 136 TIE 65 TMS 137 TIE 66 TIE 138 TIE 67 TCK 139 TIE 68 TIE 140 TIE 69 TIE 141 VCC 70 TIE 142 reset_timer 71 TIE 143 reset 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-7-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25