Release 6.1.03i - netgen G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Reading design ebeam_ctrl.nga ...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist ebeam_ctrl_timesim.vhd ...
Writing VHDL SDF file ebeam_ctrl_timesim.sdf ...
Total memory usage is 37876 kilobytes