JDF G
// Created by Project Navigator ver 1.0
PROJECT ebeam_ctrl
DESIGN ebeam
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc95288xl
DEVICETIME 1079137435
DEVPKG TQ144
DEVPKGTIME 1079137435
DEVSPEED -7
DEVSPEEDTIME 1109382612
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ebeam_ctrl.vhd
SOURCE counter32.vhd
SOURCE dff.vhd
SOURCE timelatch.vhd
SOURCE ebeammux.vhd
SOURCE timelatch_en.vhd
STIMULUS ebeammux_tbw.tbw
SOURCE edge_en.vhd
STIMULUS edge_en_tbw.tbw
STIMULUS ebeam_tbw.tbw
DEPASSOC ebeam_ctrl ebeam_ctrl.ucf
[Normal]
_SynthOpt=xstvhd, 9500xl, Schematic.t_synthesize, 1101955498, Area
[STRATEGY-LIST]
Normal=True