library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

-- ************************************************** --
-- Rev 1.1  March 12th, 2004
-- ************************************************** --


entity counter32 is
    Port ( reset 		: in std_logic;								-- reset
           clk 		: in std_logic;								-- clock
           msb_out	: out std_logic_vector(15 downto 0);	-- data
           lsb_out	: out std_logic_vector(15 downto 0)		-- data
			  );
end counter32;




architecture Behavioral of counter32 is

	signal cnt1 	: integer range 0 to 65535;	 -- lower
	signal cnt2		: integer range 0 to 65535;	 -- upper


begin

	msb_out <= CONV_STD_LOGIC_VECTOR (cnt2, 16);
	lsb_out <= CONV_STD_LOGIC_VECTOR (cnt1, 16);



	-- counter
	-------------------------------------------------------------------
	process (reset, clk, cnt1, cnt2)
	begin
		if reset = '0' then

			cnt1 <= 0;
			cnt2 <= 0;
		
		elsif ( clk'event and clk = '1' ) then


			if cnt1 < 65535 then
				cnt1 <= cnt1 +1;
				cnt2 <= cnt2;

			else
				cnt1 <= 0;

				if cnt2 < 65535 then
					cnt2 <= cnt2 + 1;
				else 
					cnt2 <= 0 ;
				end if;		

			end if;
		
		end if;

	end process;

end Behavioral;