cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: counter32 Date: 12- 1-2004, 9:44AM Device Used: XC95288XL-6-TQ144 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 33 /288 ( 11%) 145 /1440 ( 10%) 32 /288 ( 11%) 34 /117 ( 29%) 243/864 ( 28%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 0 0 | I/O : 32 77 Output : 32 32 | GCK/IO : 1 2 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 1 0 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 34 34 MACROCELL RESOURCES: Total Macrocells Available 288 Registered Macrocells 32 Non-registered Macrocell driving I/O 0 GLOBAL RESOURCES: Signal 'clk' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'reset' mapped onto global set/reset net GSR. POWER DATA: There are 33 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 33 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State _n0005/_n0005_D2 3 15 FB3_18 STD (b) (b) lsb_out<0> 3 16 FB2_6 STD FAST 12 I/O O RESET lsb_out<10> 0 0 FB9_11 STD FAST 56 I/O O RESET lsb_out<11> 0 0 FB10_17 STD FAST 129 I/O O RESET lsb_out<12> 0 0 FB4_6 STD FAST 4 I/O O RESET lsb_out<13> 0 0 FB4_14 STD FAST 7 I/O O RESET lsb_out<14> 0 0 FB8_2 STD FAST 130 I/O O RESET lsb_out<15> 0 0 FB13_2 STD FAST 71 I/O O RESET lsb_out<1> 5 16 FB2_3 STD FAST 10 I/O O RESET lsb_out<2> 6 15 FB6_8 STD FAST 139 I/O O RESET lsb_out<3> 8 16 FB6_3 STD FAST 136 I/O O RESET lsb_out<4> 6 16 FB10_8 STD FAST 121 I/O O RESET lsb_out<5> 3 16 FB2_12 STD FAST 15 I/O O RESET lsb_out<6> 0 0 FB13_14 STD FAST 76 I/O O RESET lsb_out<7> 0 0 FB5_2 STD FAST 34 I/O O RESET lsb_out<8> 0 0 FB5_10 STD FAST 39 I/O O RESET lsb_out<9> 0 0 FB5_14 STD FAST 41 I/O O RESET msb_out<0> 16 31 FB16_3 STD FAST 92 I/O O RESET msb_out<10> 3 16 FB14_3 STD FAST 100 I/O O RESET msb_out<11> 3 16 FB10_3 STD FAST 118 I/O O RESET msb_out<12> 3 16 FB14_8 STD FAST 103 I/O O RESET msb_out<13> 3 16 FB14_14 STD FAST 106 I/O O RESET msb_out<14> 3 16 FB2_17 STD FAST 19 I/O O RESET msb_out<15> 3 16 FB10_12 STD FAST 126 I/O O RESET msb_out<1> 6 17 FB1_12 STD FAST 24 I/O O RESET msb_out<2> 9 31 FB1_5 STD FAST 20 I/O O RESET msb_out<3> 11 32 FB16_8 STD FAST 95 I/O O RESET msb_out<4> 21 31 FB9_5 STD FAST 52 I/O O RESET msb_out<5> 18 31 FB15_8 STD FAST 81 I/O O RESET msb_out<6> 3 16 FB11_3 STD FAST 60 I/O O RESET msb_out<7> 3 16 FB11_12 STD FAST 68 I/O O RESET msb_out<8> 3 16 FB15_3 STD FAST 80 I/O O RESET msb_out<9> 3 16 FB12_2 STD FAST 110 I/O O RESET ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use clk FB3_10 30 GCK/I/O GCK reset FB6_15 143 GSR/I/O GSR End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 2 32 32 15 2/0 8 FB2 4 17 17 14 4/0 10 FB3 1 15 15 3 0/0 5 FB4 2 0 0 0 2/0 6 FB5 3 0 0 0 3/0 8 FB6 2 16 16 14 2/0 8 FB7 0 0 0 0 0/0 4 FB8 1 0 0 0 1/0 5 FB9 2 31 31 21 2/0 9 FB10 4 18 18 12 4/0 10 FB11 2 17 17 6 2/0 7 FB12 1 16 16 3 1/0 6 FB13 2 0 0 0 2/0 6 FB14 3 18 18 9 3/0 8 FB15 2 31 31 21 2/0 9 FB16 2 32 32 27 2/0 8 ---- ----- ----- ----- 33 145 32/0 117 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 (b) (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 \/2 3 FB1_4 (b) (b) msb_out<2> 9 4<- 0 0 FB1_5 STD 20 I/O O (unused) 0 0 /\2 3 FB1_6 21 I/O (b) (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 22 I/O (unused) 0 0 0 5 FB1_9 (b) (unused) 0 0 0 5 FB1_10 23 I/O (unused) 0 0 \/1 4 FB1_11 (b) (b) msb_out<1> 6 1<- 0 0 FB1_12 STD 24 I/O O (unused) 0 0 0 5 FB1_13 (b) (unused) 0 0 0 5 FB1_14 25 I/O (unused) 0 0 0 5 FB1_15 26 I/O (unused) 0 0 0 5 FB1_16 (b) (unused) 0 0 0 5 FB1_17 27 I/O (unused) 0 0 0 5 FB1_18 (b) Signals Used by Logic in Function Block 1: _n0005/_n0005_D2 12: lsb_out<5> 23: msb_out<15> 2: lsb_out<10> 13: lsb_out<6> 24: msb_out<1> 3: lsb_out<11> 14: lsb_out<7> 25: msb_out<2> 4: lsb_out<12> 15: lsb_out<8> 26: msb_out<3> 5: lsb_out<13> 16: lsb_out<9> 27: msb_out<4> 6: lsb_out<14> 17: msb_out<0> 28: msb_out<5> 7: lsb_out<15> 18: msb_out<10> 29: msb_out<6> 8: lsb_out<1> 19: msb_out<11> 30: msb_out<7> 9: lsb_out<2> 20: msb_out<12> 31: msb_out<8> 10: lsb_out<3> 21: msb_out<13> 32: msb_out<9> 11: lsb_out<4> 22: msb_out<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<2> XXXXXXXXXXXXXXXXXXXXXXXXX.XXXXXX........ 31 31 msb_out<1> X...............XXXXXXXXXXXXXXXX........ 17 17 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 9 I/O lsb_out<1> 5 0 0 0 FB2_3 STD 10 I/O O (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 11 I/O lsb_out<0> 3 0 0 2 FB2_6 STD 12 I/O O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 13 I/O (unused) 0 0 0 5 FB2_9 (b) (unused) 0 0 0 5 FB2_10 14 I/O (unused) 0 0 0 5 FB2_11 (b) lsb_out<5> 3 0 0 2 FB2_12 STD 15 I/O O (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 16 I/O (unused) 0 0 0 5 FB2_15 17 I/O (unused) 0 0 0 5 FB2_16 (b) msb_out<14> 3 0 0 2 FB2_17 STD 19 I/O O (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: lsb_out<0> 7: lsb_out<15> 13: lsb_out<6> 2: lsb_out<10> 8: lsb_out<1> 14: lsb_out<7> 3: lsb_out<11> 9: lsb_out<2> 15: lsb_out<8> 4: lsb_out<12> 10: lsb_out<3> 16: lsb_out<9> 5: lsb_out<13> 11: lsb_out<4> 17: msb_out<14> 6: lsb_out<14> 12: lsb_out<5> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<1> XXXXXXXXXXXXXXXX........................ 16 16 lsb_out<0> XXXXXXXXXXXXXXXX........................ 16 16 lsb_out<5> XXXXXXXXXXXXXXXX........................ 16 16 msb_out<14> .XXXXXXXXXXXXXXXX....................... 16 16 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 28 I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 (b) (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 (b) (unused) 0 0 0 5 FB3_9 (b) (unused) 0 0 0 5 FB3_10 30 GCK/I/O GCK (unused) 0 0 0 5 FB3_11 (b) (unused) 0 0 0 5 FB3_12 31 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 32 GCK/I/O (unused) 0 0 0 5 FB3_15 33 I/O (unused) 0 0 0 5 FB3_16 (b) (unused) 0 0 0 5 FB3_17 (b) _n0005/_n0005_D2 3 0 0 2 FB3_18 STD (b) (b) Signals Used by Logic in Function Block 1: lsb_out<10> 6: lsb_out<15> 11: lsb_out<5> 2: lsb_out<11> 7: lsb_out<1> 12: lsb_out<6> 3: lsb_out<12> 8: lsb_out<2> 13: lsb_out<7> 4: lsb_out<13> 9: lsb_out<3> 14: lsb_out<8> 5: lsb_out<14> 10: lsb_out<4> 15: lsb_out<9> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs _n0005/_n0005_D2 XXXXXXXXXXXXXXX......................... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 2 GTS/I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 3 GTS/I/O lsb_out<12> 0 0 0 5 FB4_6 STD 4 I/O O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 5 GTS/I/O (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 (b) (unused) 0 0 0 5 FB4_12 6 GTS/I/O (unused) 0 0 0 5 FB4_13 (b) lsb_out<13> 0 0 0 5 FB4_14 STD 7 I/O O (unused) 0 0 0 5 FB4_15 (b) (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 (b) (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<12> ........................................ 0 0 lsb_out<13> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB5_1 (b) lsb_out<7> 0 0 0 5 FB5_2 STD 34 I/O O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 35 I/O (unused) 0 0 0 5 FB5_6 (b) (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 38 GCK/I/O (unused) 0 0 0 5 FB5_9 (b) lsb_out<8> 0 0 0 5 FB5_10 STD 39 I/O O (unused) 0 0 0 5 FB5_11 (b) (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) lsb_out<9> 0 0 0 5 FB5_14 STD 41 I/O O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O (unused) 0 0 0 5 FB5_18 (b) Signals Used by Logic in Function Block Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<7> ........................................ 0 0 lsb_out<8> ........................................ 0 0 lsb_out<9> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 \/2 3 FB6_2 135 I/O (b) lsb_out<3> 8 3<- 0 0 FB6_3 STD 136 I/O O (unused) 0 0 /\1 4 FB6_4 (b) (b) (unused) 0 0 0 5 FB6_5 137 I/O (unused) 0 0 0 5 FB6_6 138 I/O (unused) 0 0 \/1 4 FB6_7 (b) (b) lsb_out<2> 6 1<- 0 0 FB6_8 STD 139 I/O O (unused) 0 0 0 5 FB6_9 (b) (unused) 0 0 0 5 FB6_10 140 I/O (unused) 0 0 0 5 FB6_11 (b) (unused) 0 0 0 5 FB6_12 (b) (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 142 I/O (unused) 0 0 0 5 FB6_15 143 GSR/I/O GSR (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 (b) (unused) 0 0 0 5 FB6_18 (b) Signals Used by Logic in Function Block 1: lsb_out<0> 7: lsb_out<15> 12: lsb_out<5> 2: lsb_out<10> 8: lsb_out<1> 13: lsb_out<6> 3: lsb_out<11> 9: lsb_out<2> 14: lsb_out<7> 4: lsb_out<12> 10: lsb_out<3> 15: lsb_out<8> 5: lsb_out<13> 11: lsb_out<4> 16: lsb_out<9> 6: lsb_out<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<3> XXXXXXXXXXXXXXXX........................ 16 16 lsb_out<2> XXXXXXXXX.XXXXXX........................ 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 (b) (unused) 0 0 0 5 FB7_3 45 I/O (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 46 I/O (unused) 0 0 0 5 FB7_6 (b) (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 (b) (unused) 0 0 0 5 FB7_9 (b) (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 (b) (unused) 0 0 0 5 FB7_12 48 I/O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 (b) (unused) 0 0 0 5 FB7_15 49 I/O (unused) 0 0 0 5 FB7_16 (b) (unused) 0 0 0 5 FB7_17 (b) (unused) 0 0 0 5 FB7_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB8_1 (b) lsb_out<14> 0 0 0 5 FB8_2 STD 130 I/O O (unused) 0 0 0 5 FB8_3 131 I/O (unused) 0 0 0 5 FB8_4 (b) (unused) 0 0 0 5 FB8_5 132 I/O (unused) 0 0 0 5 FB8_6 (b) (unused) 0 0 0 5 FB8_7 (b) (unused) 0 0 0 5 FB8_8 133 I/O (unused) 0 0 0 5 FB8_9 (b) (unused) 0 0 0 5 FB8_10 134 I/O (unused) 0 0 0 5 FB8_11 (b) (unused) 0 0 0 5 FB8_12 (b) (unused) 0 0 0 5 FB8_13 (b) (unused) 0 0 0 5 FB8_14 (b) (unused) 0 0 0 5 FB8_15 (b) (unused) 0 0 0 5 FB8_16 (b) (unused) 0 0 0 5 FB8_17 (b) (unused) 0 0 0 5 FB8_18 (b) Signals Used by Logic in Function Block Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<14> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB9 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB9_1 (b) (unused) 0 0 0 5 FB9_2 50 I/O (unused) 0 0 \/3 2 FB9_3 51 I/O (b) (unused) 0 0 \/5 0 FB9_4 (b) (b) msb_out<4> 21 16<- 0 0 FB9_5 STD 52 I/O O (unused) 0 0 /\5 0 FB9_6 53 I/O (b) (unused) 0 0 /\3 2 FB9_7 (b) (b) (unused) 0 0 0 5 FB9_8 54 I/O (unused) 0 0 0 5 FB9_9 (b) (unused) 0 0 0 5 FB9_10 (b) lsb_out<10> 0 0 0 5 FB9_11 STD 56 I/O O (unused) 0 0 0 5 FB9_12 57 I/O (unused) 0 0 0 5 FB9_13 (b) (unused) 0 0 0 5 FB9_14 58 I/O (unused) 0 0 0 5 FB9_15 (b) (unused) 0 0 0 5 FB9_16 (b) (unused) 0 0 0 5 FB9_17 59 I/O (unused) 0 0 0 5 FB9_18 (b) Signals Used by Logic in Function Block 1: lsb_out<10> 12: lsb_out<6> 22: msb_out<15> 2: lsb_out<11> 13: lsb_out<7> 23: msb_out<1> 3: lsb_out<12> 14: lsb_out<8> 24: msb_out<2> 4: lsb_out<13> 15: lsb_out<9> 25: msb_out<3> 5: lsb_out<14> 16: msb_out<0> 26: msb_out<4> 6: lsb_out<15> 17: msb_out<10> 27: msb_out<5> 7: lsb_out<1> 18: msb_out<11> 28: msb_out<6> 8: lsb_out<2> 19: msb_out<12> 29: msb_out<7> 9: lsb_out<3> 20: msb_out<13> 30: msb_out<8> 10: lsb_out<4> 21: msb_out<14> 31: msb_out<9> 11: lsb_out<5> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<4> XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX......... 31 31 lsb_out<10> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB10 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB10_1 (b) (unused) 0 0 0 5 FB10_2 117 I/O msb_out<11> 3 0 0 2 FB10_3 STD 118 I/O O (unused) 0 0 0 5 FB10_4 (b) (unused) 0 0 0 5 FB10_5 119 I/O (unused) 0 0 0 5 FB10_6 120 I/O (unused) 0 0 \/1 4 FB10_7 (b) (b) lsb_out<4> 6 1<- 0 0 FB10_8 STD 121 I/O O (unused) 0 0 0 5 FB10_9 (b) (unused) 0 0 0 5 FB10_10 124 I/O (unused) 0 0 0 5 FB10_11 125 I/O msb_out<15> 3 0 0 2 FB10_12 STD 126 I/O O (unused) 0 0 0 5 FB10_13 (b) (unused) 0 0 0 5 FB10_14 128 I/O (unused) 0 0 0 5 FB10_15 (b) (unused) 0 0 0 5 FB10_16 (b) lsb_out<11> 0 0 0 5 FB10_17 STD 129 I/O O (unused) 0 0 0 5 FB10_18 (b) Signals Used by Logic in Function Block 1: lsb_out<0> 7: lsb_out<15> 13: lsb_out<6> 2: lsb_out<10> 8: lsb_out<1> 14: lsb_out<7> 3: lsb_out<11> 9: lsb_out<2> 15: lsb_out<8> 4: lsb_out<12> 10: lsb_out<3> 16: lsb_out<9> 5: lsb_out<13> 11: lsb_out<4> 17: msb_out<11> 6: lsb_out<14> 12: lsb_out<5> 18: msb_out<15> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<11> .XXXXXXXXXXXXXXXX....................... 16 16 lsb_out<4> XXXXXXXXXXXXXXXX........................ 16 16 msb_out<15> .XXXXXXXXXXXXXXX.X...................... 16 16 lsb_out<11> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB11 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB11_1 (b) (unused) 0 0 0 5 FB11_2 (b) msb_out<6> 3 0 0 2 FB11_3 STD 60 I/O O (unused) 0 0 0 5 FB11_4 (b) (unused) 0 0 0 5 FB11_5 61 I/O (unused) 0 0 0 5 FB11_6 (b) (unused) 0 0 0 5 FB11_7 (b) (unused) 0 0 0 5 FB11_8 (b) (unused) 0 0 0 5 FB11_9 (b) (unused) 0 0 0 5 FB11_10 64 I/O (unused) 0 0 0 5 FB11_11 66 I/O msb_out<7> 3 0 0 2 FB11_12 STD 68 I/O O (unused) 0 0 0 5 FB11_13 (b) (unused) 0 0 0 5 FB11_14 69 I/O (unused) 0 0 0 5 FB11_15 (b) (unused) 0 0 0 5 FB11_16 (b) (unused) 0 0 0 5 FB11_17 70 I/O (unused) 0 0 0 5 FB11_18 (b) Signals Used by Logic in Function Block 1: lsb_out<10> 7: lsb_out<1> 13: lsb_out<7> 2: lsb_out<11> 8: lsb_out<2> 14: lsb_out<8> 3: lsb_out<12> 9: lsb_out<3> 15: lsb_out<9> 4: lsb_out<13> 10: lsb_out<4> 16: msb_out<6> 5: lsb_out<14> 11: lsb_out<5> 17: msb_out<7> 6: lsb_out<15> 12: lsb_out<6> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<6> XXXXXXXXXXXXXXXX........................ 16 16 msb_out<7> XXXXXXXXXXXXXXX.X....................... 16 16 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB12 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB12_1 (b) msb_out<9> 3 0 0 2 FB12_2 STD 110 I/O O (unused) 0 0 0 5 FB12_3 111 I/O (unused) 0 0 0 5 FB12_4 (b) (unused) 0 0 0 5 FB12_5 112 I/O (unused) 0 0 0 5 FB12_6 (b) (unused) 0 0 0 5 FB12_7 (b) (unused) 0 0 0 5 FB12_8 113 I/O (unused) 0 0 0 5 FB12_9 (b) (unused) 0 0 0 5 FB12_10 115 I/O (unused) 0 0 0 5 FB12_11 (b) (unused) 0 0 0 5 FB12_12 116 I/O (unused) 0 0 0 5 FB12_13 (b) (unused) 0 0 0 5 FB12_14 (b) (unused) 0 0 0 5 FB12_15 (b) (unused) 0 0 0 5 FB12_16 (b) (unused) 0 0 0 5 FB12_17 (b) (unused) 0 0 0 5 FB12_18 (b) Signals Used by Logic in Function Block 1: lsb_out<10> 7: lsb_out<1> 12: lsb_out<6> 2: lsb_out<11> 8: lsb_out<2> 13: lsb_out<7> 3: lsb_out<12> 9: lsb_out<3> 14: lsb_out<8> 4: lsb_out<13> 10: lsb_out<4> 15: lsb_out<9> 5: lsb_out<14> 11: lsb_out<5> 16: msb_out<9> 6: lsb_out<15> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<9> XXXXXXXXXXXXXXXX........................ 16 16 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB13 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB13_1 (b) lsb_out<15> 0 0 0 5 FB13_2 STD 71 I/O O (unused) 0 0 0 5 FB13_3 (b) (unused) 0 0 0 5 FB13_4 (b) (unused) 0 0 0 5 FB13_5 (b) (unused) 0 0 0 5 FB13_6 (b) (unused) 0 0 0 5 FB13_7 (b) (unused) 0 0 0 5 FB13_8 74 I/O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) (unused) 0 0 0 5 FB13_11 75 I/O (unused) 0 0 0 5 FB13_12 (b) (unused) 0 0 0 5 FB13_13 (b) lsb_out<6> 0 0 0 5 FB13_14 STD 76 I/O O (unused) 0 0 0 5 FB13_15 77 I/O (unused) 0 0 0 5 FB13_16 (b) (unused) 0 0 0 5 FB13_17 78 I/O (unused) 0 0 0 5 FB13_18 (b) Signals Used by Logic in Function Block Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs lsb_out<15> ........................................ 0 0 lsb_out<6> ........................................ 0 0 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB14 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB14_1 (b) (unused) 0 0 0 5 FB14_2 (b) msb_out<10> 3 0 0 2 FB14_3 STD 100 I/O O (unused) 0 0 0 5 FB14_4 (b) (unused) 0 0 0 5 FB14_5 101 I/O (unused) 0 0 0 5 FB14_6 102 I/O (unused) 0 0 0 5 FB14_7 (b) msb_out<12> 3 0 0 2 FB14_8 STD 103 I/O O (unused) 0 0 0 5 FB14_9 (b) (unused) 0 0 0 5 FB14_10 104 I/O (unused) 0 0 0 5 FB14_11 105 I/O (unused) 0 0 0 5 FB14_12 (b) (unused) 0 0 0 5 FB14_13 (b) msb_out<13> 3 0 0 2 FB14_14 STD 106 I/O O (unused) 0 0 0 5 FB14_15 107 I/O (unused) 0 0 0 5 FB14_16 (b) (unused) 0 0 0 5 FB14_17 (b) (unused) 0 0 0 5 FB14_18 (b) Signals Used by Logic in Function Block 1: lsb_out<10> 7: lsb_out<1> 13: lsb_out<7> 2: lsb_out<11> 8: lsb_out<2> 14: lsb_out<8> 3: lsb_out<12> 9: lsb_out<3> 15: lsb_out<9> 4: lsb_out<13> 10: lsb_out<4> 16: msb_out<10> 5: lsb_out<14> 11: lsb_out<5> 17: msb_out<12> 6: lsb_out<15> 12: lsb_out<6> 18: msb_out<13> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<10> XXXXXXXXXXXXXXXX........................ 16 16 msb_out<12> XXXXXXXXXXXXXXX.X....................... 16 16 msb_out<13> XXXXXXXXXXXXXXX..X...................... 16 16 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB15 *********************************** Number of function block inputs used/remaining: 31/23 Number of signals used by logic mapping into function block: 31 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB15_1 (b) (unused) 0 0 0 5 FB15_2 79 I/O msb_out<8> 3 0 0 2 FB15_3 STD 80 I/O O (unused) 0 0 0 5 FB15_4 (b) (unused) 0 0 0 5 FB15_5 (b) (unused) 0 0 \/2 3 FB15_6 (b) (b) (unused) 0 0 \/5 0 FB15_7 (b) (b) msb_out<5> 18 13<- 0 0 FB15_8 STD 81 I/O O (unused) 0 0 /\5 0 FB15_9 (b) (b) (unused) 0 0 /\1 4 FB15_10 82 I/O (b) (unused) 0 0 0 5 FB15_11 83 I/O (unused) 0 0 0 5 FB15_12 85 I/O (unused) 0 0 0 5 FB15_13 (b) (unused) 0 0 0 5 FB15_14 86 I/O (unused) 0 0 0 5 FB15_15 87 I/O (unused) 0 0 0 5 FB15_16 (b) (unused) 0 0 0 5 FB15_17 88 I/O (unused) 0 0 0 5 FB15_18 (b) Signals Used by Logic in Function Block 1: lsb_out<10> 12: lsb_out<6> 22: msb_out<15> 2: lsb_out<11> 13: lsb_out<7> 23: msb_out<1> 3: lsb_out<12> 14: lsb_out<8> 24: msb_out<2> 4: lsb_out<13> 15: lsb_out<9> 25: msb_out<3> 5: lsb_out<14> 16: msb_out<0> 26: msb_out<4> 6: lsb_out<15> 17: msb_out<10> 27: msb_out<5> 7: lsb_out<1> 18: msb_out<11> 28: msb_out<6> 8: lsb_out<2> 19: msb_out<12> 29: msb_out<7> 9: lsb_out<3> 20: msb_out<13> 30: msb_out<8> 10: lsb_out<4> 21: msb_out<14> 31: msb_out<9> 11: lsb_out<5> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<8> XXXXXXXXXXXXXXX..............X.......... 16 16 msb_out<5> XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX......... 31 31 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB16 *********************************** Number of function block inputs used/remaining: 32/22 Number of signals used by logic mapping into function block: 32 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 \/1 4 FB16_1 (b) (b) (unused) 0 0 \/5 0 FB16_2 91 I/O (b) msb_out<0> 16 11<- 0 0 FB16_3 STD 92 I/O O (unused) 0 0 /\5 0 FB16_4 (b) (b) (unused) 0 0 0 5 FB16_5 93 I/O (unused) 0 0 0 5 FB16_6 94 I/O (unused) 0 0 \/3 2 FB16_7 (b) (b) msb_out<3> 11 6<- 0 0 FB16_8 STD 95 I/O O (unused) 0 0 /\3 2 FB16_9 (b) (b) (unused) 0 0 0 5 FB16_10 96 I/O (unused) 0 0 0 5 FB16_11 97 I/O (unused) 0 0 0 5 FB16_12 98 I/O (unused) 0 0 0 5 FB16_13 (b) (unused) 0 0 0 5 FB16_14 (b) (unused) 0 0 0 5 FB16_15 (b) (unused) 0 0 0 5 FB16_16 (b) (unused) 0 0 0 5 FB16_17 (b) (unused) 0 0 0 5 FB16_18 (b) Signals Used by Logic in Function Block 1: _n0005/_n0005_D2 12: lsb_out<5> 23: msb_out<15> 2: lsb_out<10> 13: lsb_out<6> 24: msb_out<1> 3: lsb_out<11> 14: lsb_out<7> 25: msb_out<2> 4: lsb_out<12> 15: lsb_out<8> 26: msb_out<3> 5: lsb_out<13> 16: lsb_out<9> 27: msb_out<4> 6: lsb_out<14> 17: msb_out<0> 28: msb_out<5> 7: lsb_out<15> 18: msb_out<10> 29: msb_out<6> 8: lsb_out<1> 19: msb_out<11> 30: msb_out<7> 9: lsb_out<2> 20: msb_out<12> 31: msb_out<8> 10: lsb_out<3> 21: msb_out<13> 32: msb_out<9> 11: lsb_out<4> 22: msb_out<14> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs msb_out<0> .XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX........ 31 31 msb_out<3> XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX........ 32 32 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. _n0005/_n0005_D2 = !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<0>.D = !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<0>.CLK = clk; // GCK !lsb_out<0>.AR = reset; // GSR lsb_out<10>.D = Gnd; lsb_out<10>.CLK = clk; // GCK !lsb_out<10>.AR = reset; // GSR lsb_out<11>.D = Gnd; lsb_out<11>.CLK = clk; // GCK !lsb_out<11>.AR = reset; // GSR lsb_out<12>.D = Gnd; lsb_out<12>.CLK = clk; // GCK !lsb_out<12>.AR = reset; // GSR lsb_out<13>.D = Gnd; lsb_out<13>.CLK = clk; // GCK !lsb_out<13>.AR = reset; // GSR lsb_out<14>.D = Gnd; lsb_out<14>.CLK = clk; // GCK !lsb_out<14>.AR = reset; // GSR lsb_out<15>.D = Gnd; lsb_out<15>.CLK = clk; // GCK !lsb_out<15>.AR = reset; // GSR lsb_out<1>.D = lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<1>.CLK = clk; // GCK !lsb_out<1>.AR = reset; // GSR lsb_out<2>.D = !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<2> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<2> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & lsb_out<2> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & lsb_out<2> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & !lsb_out<2> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB6_7 # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & !lsb_out<2> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<2>.CLK = clk; // GCK !lsb_out<2>.AR = reset; // GSR lsb_out<3>.D = !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<3> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & lsb_out<3> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & lsb_out<3> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<2> & lsb_out<3> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<2> & lsb_out<3> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB6_2 # !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<3> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & lsb_out<2> & !lsb_out<3> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB6_4 # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & lsb_out<2> & !lsb_out<3> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<3>.CLK = clk; // GCK !lsb_out<3>.AR = reset; // GSR lsb_out<4>.D = !lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<4> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & lsb_out<4> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<2> & lsb_out<4> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<3> & lsb_out<4> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB10_7 # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & lsb_out<2> & lsb_out<3> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<4>.CLK = clk; // GCK !lsb_out<4>.AR = reset; // GSR lsb_out<5>.D = !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # lsb_out<0> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & lsb_out<1> & lsb_out<2> & lsb_out<3> & lsb_out<4> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; lsb_out<5>.CLK = clk; // GCK !lsb_out<5>.AR = reset; // GSR lsb_out<6>.D = Gnd; lsb_out<6>.CLK = clk; // GCK !lsb_out<6>.AR = reset; // GSR lsb_out<7>.D = Gnd; lsb_out<7>.CLK = clk; // GCK !lsb_out<7>.AR = reset; // GSR lsb_out<8>.D = Gnd; lsb_out<8>.CLK = clk; // GCK !lsb_out<8>.AR = reset; // GSR lsb_out<9>.D = Gnd; lsb_out<9>.CLK = clk; // GCK !lsb_out<9>.AR = reset; // GSR !msb_out<0>.T = !msb_out<0> & msb_out<11> # !msb_out<0> & msb_out<13> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB16_2 # !msb_out<0> & msb_out<10> # !msb_out<0> & msb_out<12> # !msb_out<0> & msb_out<14> # !msb_out<0> & msb_out<6> # !msb_out<0> & msb_out<15> ;Imported pterms FB16_1 # !msb_out<0> & msb_out<3> & msb_out<4> & msb_out<5> ;Imported pterms FB16_4 # !msb_out<0> & msb_out<7> # !msb_out<0> & msb_out<8> # !msb_out<0> & msb_out<9> # !msb_out<0> & msb_out<1> & msb_out<4> & msb_out<5> # !msb_out<0> & msb_out<2> & msb_out<4> & msb_out<5>; msb_out<0>.CLK = clk; // GCK !msb_out<0>.AR = reset; // GSR msb_out<10>.D = msb_out<10> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<10> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<10> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<10>.CLK = clk; // GCK !msb_out<10>.AR = reset; // GSR msb_out<11>.D = msb_out<11> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<11> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<11> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<11>.CLK = clk; // GCK !msb_out<11>.AR = reset; // GSR msb_out<12>.D = msb_out<12> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<12> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<12> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<12>.CLK = clk; // GCK !msb_out<12>.AR = reset; // GSR msb_out<13>.D = msb_out<13> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<13> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<13> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<13>.CLK = clk; // GCK !msb_out<13>.AR = reset; // GSR msb_out<14>.D = msb_out<14> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<14> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<14> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<14>.CLK = clk; // GCK !msb_out<14>.AR = reset; // GSR msb_out<15>.D = msb_out<15> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<15> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<15> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<15>.CLK = clk; // GCK !msb_out<15>.AR = reset; // GSR msb_out<1>.D = msb_out<1> & _n0005/_n0005_D2 # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2 ;Imported pterms FB1_11 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & !msb_out<2> & !msb_out<3> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2; msb_out<1>.CLK = clk; // GCK !msb_out<1>.AR = reset; // GSR msb_out<2>.D = msb_out<2> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<2> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<2> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & msb_out<2> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & msb_out<2> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> ;Imported pterms FB1_4 # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<2> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # msb_out<2> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB1_6 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & !msb_out<2> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & !msb_out<2> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2; msb_out<2>.CLK = clk; // GCK !msb_out<2>.AR = reset; // GSR msb_out<3>.D = msb_out<3> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<3> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & msb_out<3> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> ;Imported pterms FB16_7 # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<3> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<2> & msb_out<3> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> ;Imported pterms FB16_9 # msb_out<3> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & !msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & !msb_out<3> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & !_n0005/_n0005_D2; msb_out<3>.CLK = clk; // GCK !msb_out<3>.AR = reset; // GSR msb_out<4>.D = !msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<2> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & !msb_out<2> & !msb_out<3> & msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> ;Imported pterms FB9_4 # msb_out<4> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<4> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<4> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<11> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<13> ;Imported pterms FB9_3 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<7> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<8> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<9> ;Imported pterms FB9_6 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<10> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<12> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<14> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<6> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<15> ;Imported pterms FB9_7 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<1> & lsb_out<4> & lsb_out<5> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<2> & lsb_out<4> & lsb_out<5> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & !msb_out<4> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<3> & lsb_out<4> & lsb_out<5>; msb_out<4>.CLK = clk; // GCK !msb_out<4>.AR = reset; // GSR msb_out<5>.D = !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<4> & msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # msb_out<5> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<5> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & !msb_out<1> & !msb_out<2> & !msb_out<3> & msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> # msb_out<5> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> ;Imported pterms FB15_7 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<10> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<11> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<12> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<13> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<14> ;Imported pterms FB15_6 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<1> & lsb_out<4> & lsb_out<5> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<2> & lsb_out<4> & lsb_out<5> ;Imported pterms FB15_9 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<6> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<7> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<8> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<9> # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<15> ;Imported pterms FB15_10 # msb_out<0> & !msb_out<10> & !msb_out<11> & !msb_out<12> & !msb_out<13> & !msb_out<14> & msb_out<1> & msb_out<2> & msb_out<3> & msb_out<4> & !msb_out<5> & !msb_out<6> & !msb_out<7> & !msb_out<8> & !msb_out<9> & !msb_out<15> & lsb_out<3> & lsb_out<4> & lsb_out<5>; msb_out<5>.CLK = clk; // GCK !msb_out<5>.AR = reset; // GSR msb_out<6>.D = msb_out<6> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<6> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<6> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<6>.CLK = clk; // GCK !msb_out<6>.AR = reset; // GSR msb_out<7>.D = msb_out<7> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<7> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<7> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<7>.CLK = clk; // GCK !msb_out<7>.AR = reset; // GSR msb_out<8>.D = msb_out<8> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<8> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<8> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<8>.CLK = clk; // GCK !msb_out<8>.AR = reset; // GSR msb_out<9>.D = msb_out<9> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<4> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<9> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<5> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15> # msb_out<9> & !lsb_out<10> & !lsb_out<11> & !lsb_out<12> & !lsb_out<13> & !lsb_out<14> & !lsb_out<1> & !lsb_out<2> & !lsb_out<3> & !lsb_out<6> & !lsb_out<7> & !lsb_out<8> & !lsb_out<9> & !lsb_out<15>; msb_out<9>.CLK = clk; // GCK !msb_out<9>.AR = reset; // GSR Legend: .COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC95288XL-6-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 TIE 74 TIE 3 TIE 75 TIE 4 lsb_out<12> 76 lsb_out<6> 5 TIE 77 TIE 6 TIE 78 TIE 7 lsb_out<13> 79 TIE 8 VCC 80 msb_out<8> 9 TIE 81 msb_out<5> 10 lsb_out<1> 82 TIE 11 TIE 83 TIE 12 lsb_out<0> 84 VCC 13 TIE 85 TIE 14 TIE 86 TIE 15 lsb_out<5> 87 TIE 16 TIE 88 TIE 17 TIE 89 GND 18 GND 90 GND 19 msb_out<14> 91 TIE 20 msb_out<2> 92 msb_out<0> 21 TIE 93 TIE 22 TIE 94 TIE 23 TIE 95 msb_out<3> 24 msb_out<1> 96 TIE 25 TIE 97 TIE 26 TIE 98 TIE 27 TIE 99 GND 28 TIE 100 msb_out<10> 29 GND 101 TIE 30 clk 102 TIE 31 TIE 103 msb_out<12> 32 TIE 104 TIE 33 TIE 105 TIE 34 lsb_out<7> 106 msb_out<13> 35 TIE 107 TIE 36 GND 108 GND 37 VCC 109 VCC 38 TIE 110 msb_out<9> 39 lsb_out<8> 111 TIE 40 TIE 112 TIE 41 lsb_out<9> 113 TIE 42 VCC 114 GND 43 TIE 115 TIE 44 TIE 116 TIE 45 TIE 117 TIE 46 TIE 118 msb_out<11> 47 GND 119 TIE 48 TIE 120 TIE 49 TIE 121 lsb_out<4> 50 TIE 122 TDO 51 TIE 123 GND 52 msb_out<4> 124 TIE 53 TIE 125 TIE 54 TIE 126 msb_out<15> 55 VCC 127 VCC 56 lsb_out<10> 128 TIE 57 TIE 129 lsb_out<11> 58 TIE 130 lsb_out<14> 59 TIE 131 TIE 60 msb_out<6> 132 TIE 61 TIE 133 TIE 62 GND 134 TIE 63 TDI 135 TIE 64 TIE 136 lsb_out<3> 65 TMS 137 TIE 66 TIE 138 TIE 67 TCK 139 lsb_out<2> 68 msb_out<7> 140 TIE 69 TIE 141 VCC 70 TIE 142 TIE 71 lsb_out<15> 143 reset 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-6-TQ144 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25