Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 28. Undefined symbol 'msb'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 28. msb: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 28. Undefined symbol 'lsb'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 28. lsb: Undefined symbol (last report in this block) ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 154. Index size for dimension 1 of msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 155. Index size for dimension 1 of lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 156. Index size for dimension 1 of s_msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 157. Index size for dimension 1 of s_lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 164. Index size for dimension 1 of msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 165. Index size for dimension 1 of lsb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 166. Index size for dimension 1 of s_msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 167. Index size for dimension 1 of s_lsb_2 is not 16. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 177. Undefined symbol 'msb1'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 177. msb1: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 178. Undefined symbol 'lsb1'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 178. lsb1: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 179. Undefined symbol 'msb2'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 179. msb2: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 180. Undefined symbol 'lsb2'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 180. lsb2: Undefined symbol (last report in this block) ERROR:HDLParsers:850 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 175. Formal port upper does not exist in Component 'ebeammux'. ERROR:HDLParsers:850 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 176. Formal port lower does not exist in Component 'ebeammux'. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 154. Index size for dimension 1 of msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 155. Index size for dimension 1 of lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 156. Index size for dimension 1 of s_msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 157. Index size for dimension 1 of s_lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 164. Index size for dimension 1 of msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 165. Index size for dimension 1 of lsb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 166. Index size for dimension 1 of s_msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 167. Index size for dimension 1 of s_lsb_2 is not 16. ERROR:HDLParsers:850 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 175. Formal port upper does not exist in Component 'ebeammux'. ERROR:HDLParsers:850 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 176. Formal port lower does not exist in Component 'ebeammux'. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 156. Index size for dimension 1 of msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 157. Index size for dimension 1 of lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 158. Index size for dimension 1 of s_msb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 159. Index size for dimension 1 of s_lsb_1 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 166. Index size for dimension 1 of msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 167. Index size for dimension 1 of lsb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 168. Index size for dimension 1 of s_msb_2 is not 16. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 169. Index size for dimension 1 of s_lsb_2 is not 16. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 119 # Stopped at ebeam_tbw.ant line 119 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 122 # Stopped at ebeam_tbw.ant line 122 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 125 # Stopped at ebeam_tbw.ant line 125 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 157 # Stopped at ebeam_tbw.ant line 157 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1161 ns Iteration: 0 Process: /ebeam_tbw/line__98 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 149 # Stopped at ebeam_tbw.ant line 149 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__136 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 158 # Stopped at ebeam_tbw.ant line 158 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__117 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 134 # Stopped at ebeam_tbw.ant line 134 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__117 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 134 # Stopped at ebeam_tbw.ant line 134 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:3313 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 116. Undefined symbol 'falling'. Should it be: faliing? Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # ** Error: ebeam_ctrl.vhd(116): Illegal target for signal assignment. # ** Error: ebeam_ctrl.vhd(116): Unknown identifier: falling # ** Error: ebeam_ctrl.vhd(116): Target of signal assignment is not a signal. # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # ** Error: ebeam_ctrl.vhd(190): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./ebeam_tbw.ado line 15 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__157 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 174 # Stopped at ebeam_tbw.ant line 174 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2400 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3006 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3906 ns Iteration: 0 Process: /ebeam_tbw/line__177 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 194 # Stopped at ebeam_tbw.ant line 194 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd. Found 15-bit register for signal . Found 15-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 15-bit register for signal . Found 15-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd. Found 15-bit comparator less for signal <$n0005> created at line 55. Found 15-bit comparator less for signal <$n0006> created at line 62. Found 15-bit adder for signal <$n0007> created at line 56. Found 15-bit adder for signal <$n0008> created at line 63. Found 15-bit register for signal . Found 15-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 15-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 15-bit adder : 2 # Comparators : 2 15-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_10 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 170 but only 144 left after allocating other resources. Device 95144XL100 was disqualified. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 170 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 170 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 170 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 170 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Insufficient number of macrocells. The design needs at least 170 but only 72 left after allocating other resources. Device XC9572XL-5-PC44 was disqualified. Considering device XC9572XL-5-VQ44. Insufficient number of macrocells. The design needs at least 170 but only 72 left after allocating other resources. Device XC9572XL-5-VQ44 was disqualified. Considering device XC9572XL-5-CS48. Insufficient number of macrocells. The design needs at least 170 but only 72 left after allocating other resources. Device XC9572XL-5-CS48 was disqualified. Considering device XC9572XL-5-VQ64. Insufficient number of macrocells. The design needs at least 170 but only 72 left after allocating other resources. Device XC9572XL-5-VQ64 was disqualified. Considering device XC9572XL-5-TQ100. Insufficient number of macrocells. The design needs at least 170 but only 72 left after allocating other resources. Device XC9572XL-5-TQ100 was disqualified. Considering device XC95144XL-5-TQ100. Insufficient number of macrocells. The design needs at least 170 but only 144 left after allocating other resources. Device XC95144XL-5-TQ100 was disqualified. Considering device XC95144XL-5-CS144. Insufficient number of macrocells. The design needs at least 170 but only 144 left after allocating other resources. Device XC95144XL-5-CS144 was disqualified. Considering device XC95144XL-5-TQ144. Insufficient number of macrocells. The design needs at least 170 but only 144 left after allocating other resources. Device XC95144XL-5-TQ144 was disqualified. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 170 equations into 16 function blocks...................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 912. ..... The number of paths traced: 1825. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock clk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 112. Undefined symbol 'rising'. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 113. Undefined symbol 'falling'. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 114. Undefined symbol 'time1val'. --> Total memory usage is 44540 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd in Library work. Architecture behavioral of Entity counter30 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd in Library work. Architecture behavioral of Entity systimelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/systimelatch.vhd. Found 15-bit register for signal . Found 15-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 15-bit register for signal . Found 15-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter30.vhd. Found 15-bit comparator less for signal <$n0005> created at line 55. Found 15-bit comparator less for signal <$n0006> created at line 62. Found 15-bit adder for signal <$n0007> created at line 56. Found 15-bit adder for signal <$n0008> created at line 63. Found 15-bit register for signal . Found 15-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 15-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 15-bit adder : 2 # Comparators : 2 15-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_10 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 168 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 168 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 168 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 168 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Insufficient number of macrocells. The design needs at least 168 but only 72 left after allocating other resources. Device XC9572XL-5-PC44 was disqualified. Considering device XC9572XL-5-VQ44. Insufficient number of macrocells. The design needs at least 168 but only 72 left after allocating other resources. Device XC9572XL-5-VQ44 was disqualified. Considering device XC9572XL-5-CS48. Insufficient number of macrocells. The design needs at least 168 but only 72 left after allocating other resources. Device XC9572XL-5-CS48 was disqualified. Considering device XC9572XL-5-VQ64. Insufficient number of macrocells. The design needs at least 168 but only 72 left after allocating other resources. Device XC9572XL-5-VQ64 was disqualified. Considering device XC9572XL-5-TQ100. Insufficient number of macrocells. The design needs at least 168 but only 72 left after allocating other resources. Device XC9572XL-5-TQ100 was disqualified. Considering device XC95144XL-5-TQ100. Insufficient number of macrocells. The design needs at least 168 but only 144 left after allocating other resources. Device XC95144XL-5-TQ100 was disqualified. Considering device XC95144XL-5-CS144. Insufficient number of macrocells. The design needs at least 168 but only 144 left after allocating other resources. Device XC95144XL-5-CS144 was disqualified. Considering device XC95144XL-5-TQ144. Insufficient number of macrocells. The design needs at least 168 but only 144 left after allocating other resources. Device XC95144XL-5-TQ144 was disqualified. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 168 equations into 16 function blocks.............................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 876. .... The number of paths traced: 1753. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock clk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 168 equations into 16 function blocks.............................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ......... The number of paths traced: 876. .... The number of paths traced: 1753. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock clk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # Loading work.counter30(behavioral) # Loading work.timelatch(behavioral) # Loading work.systimelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 3906 ns Iteration: 0 Process: /ebeam_tbw/line__117 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 134 # Stopped at ebeam_tbw.ant line 134 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter30 # -- Compiling architecture behavioral of counter30 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter30 # WARNING[1]: ebeam_ctrl.vhd(128): Length of entity port is 16. Length of msb_out is 15. # WARNING[1]: ebeam_ctrl.vhd(128): A use of this default binding for this component instantiation will result in an elaboration error. # WARNING[1]: ebeam_ctrl.vhd(128): Length of entity port is 16. Length of lsb_out is 15. # WARNING[1]: ebeam_ctrl.vhd(128): A use of this default binding for this component instantiation will result in an elaboration error. # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # ** Failure: Default binding had errors for entity "counter30" on the component declaration of line 128. See the compiler messages. # Time: 0 ps Iteration: 0 Instance: /ebeam_tbw/uut File: ebeam_ctrl.vhd # Loading work.timelatch(behavioral) # Fatal error at timelatch.vhd line 34 # while elaborating region: /ebeam_tbw/uut/inst_timelatch_1 # Load interrupted # Error loading design Error loading design ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity systimelatch # -- Compiling architecture behavioral of systimelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity dff # -- Loading entity counter32 # WARNING[1]: ebeam_ctrl.vhd(128): Length of entity port is 16. Length of msb_out is 15. # WARNING[1]: ebeam_ctrl.vhd(128): A use of this default binding for this component instantiation will result in an elaboration error. # WARNING[1]: ebeam_ctrl.vhd(128): Length of entity port is 16. Length of lsb_out is 15. # WARNING[1]: ebeam_ctrl.vhd(128): A use of this default binding for this component instantiation will result in an elaboration error. # -- Loading entity timelatch # -- Loading entity systimelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.dff(behavioral) # ** Failure: Default binding had errors for entity "counter32" on the component declaration of line 128. See the compiler messages. # Time: 0 ps Iteration: 0 Instance: /ebeam_tbw/uut File: ebeam_ctrl.vhd # Loading work.timelatch(behavioral) # Fatal error at timelatch.vhd line 34 # while elaborating region: /ebeam_tbw/uut/inst_timelatch_1 # Load interrupted # Error loading design Error loading design ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 109. Index size for dimension 1 of cnt_msb is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 110. Index size for dimension 1 of cnt_lsb is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 111. Index size for dimension 1 of msb1 is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 112. Index size for dimension 1 of lsb1 is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 119. Index size for dimension 1 of cnt_msb is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 120. Index size for dimension 1 of cnt_lsb is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 121. Index size for dimension 1 of msb2 is not 15. ERROR:HDLParsers:837 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 122. Index size for dimension 1 of lsb2 is not 15. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. ERROR:HDLParsers:3384 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd Line 35. String Literal "000000000000000" is not of size 16. ERROR:HDLParsers:3384 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd Line 36. String Literal "000000000000000" is not of size 16. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. ERROR:HDLParsers:3384 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd Line 35. String Literal "000000000000000" is not of size 16. ERROR:HDLParsers:3384 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd Line 36. String Literal "000000000000000" is not of size 16. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 5556 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__176 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 198 # Stopped at ebeam_ctrl_tbw.ant line 198 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1512 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__120 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 139 # Stopped at ebeam_ctrl_tbw.ant line 139 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__180 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 198 # Stopped at ebeam_ctrl_tbw.ant line 198 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # ** Error: timelatch.vhd(31): Unknown identifier: latch_en # ** Error: timelatch.vhd(31): Expression is not a signal. # ** Error: timelatch.vhd(49): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./ebeam_ctrl_tbw.ado line 12 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__180 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 198 # Stopped at ebeam_ctrl_tbw.ant line 198 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__219 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 237 # Stopped at ebeam_ctrl_tbw.ant line 237 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__219 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 237 # Stopped at ebeam_ctrl_tbw.ant line 237 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__219 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 237 # Stopped at ebeam_ctrl_tbw.ant line 237 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__222 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 240 # Stopped at ebeam_ctrl_tbw.ant line 240 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__222 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 240 # Stopped at ebeam_ctrl_tbw.ant line 240 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 55. Found 16-bit comparator less for signal <$n0006> created at line 62. Found 16-bit adder for signal <$n0007> created at line 56. Found 16-bit adder for signal <$n0008> created at line 63. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 7 16-bit register : 6 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC9536XL-5-PC44. Insufficient number of macrocells. The design needs at least 115 but only 36 left after allocating other resources. Device XC9536XL-5-PC44 was disqualified. Considering device XC9536XL-5-VQ44. Insufficient number of macrocells. The design needs at least 115 but only 36 left after allocating other resources. Device XC9536XL-5-VQ44 was disqualified. Considering device XC9536XL-5-CS48. Insufficient number of macrocells. The design needs at least 115 but only 36 left after allocating other resources. Device XC9536XL-5-CS48 was disqualified. Considering device XC9536XL-5-VQ64. Insufficient number of macrocells. The design needs at least 115 but only 36 left after allocating other resources. Device XC9536XL-5-VQ64 was disqualified. Considering device XC9572XL-5-PC44. Insufficient number of macrocells. The design needs at least 115 but only 72 left after allocating other resources. Device XC9572XL-5-PC44 was disqualified. Considering device XC9572XL-5-VQ44. Insufficient number of macrocells. The design needs at least 115 but only 72 left after allocating other resources. Device XC9572XL-5-VQ44 was disqualified. Considering device XC9572XL-5-CS48. Insufficient number of macrocells. The design needs at least 115 but only 72 left after allocating other resources. Device XC9572XL-5-CS48 was disqualified. Considering device XC9572XL-5-VQ64. Insufficient number of macrocells. The design needs at least 115 but only 72 left after allocating other resources. Device XC9572XL-5-VQ64 was disqualified. Considering device XC9572XL-5-TQ100. Insufficient number of macrocells. The design needs at least 115 but only 72 left after allocating other resources. Device XC9572XL-5-TQ100 was disqualified. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 116 equations into 8 function blocks............................................................ Design ebeam_ctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1029. ..... The number of paths traced: 2059. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 116 equations into 8 function blocks............................................................ Design ebeam_ctrl has been optimized and fit into device XC95144XL-5-TQ100. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing .......... The number of paths traced: 1029. ..... The number of paths traced: 2059. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 35704 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__244 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 262 # Stopped at ebeam_ctrl_tbw.ant line 262 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__240 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 258 # Stopped at ebeam_ctrl_tbw.ant line 258 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # ** Error: ebeam_ctrl.vhd(154): Unknown identifier: clk # ** Error: ebeam_ctrl.vhd(154): Unknown identifier: clk # -- Loading entity timelatch_en # ** Error: ebeam_ctrl.vhd(164): Unknown identifier: clk # ** Error: ebeam_ctrl.vhd(164): Unknown identifier: clk # -- Loading entity ebeammux # ** Error: ebeam_ctrl.vhd(185): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./ebeam_ctrl_tbw.ado line 15 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 7356 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__244 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 262 # Stopped at ebeam_ctrl_tbw.ant line 262 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 8856 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__298 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 316 # Stopped at ebeam_ctrl_tbw.ant line 316 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34444 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95144XL-5-TQ100. Flattening design.. Multi-level logic optimization... Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 180 but only 144 left after allocating other resources. Device 95144XL100 was disqualified. ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options. ERROR: Fit failed Reason: Process "Fit" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 180 equations into 16 function blocks........................................................................................ Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1238. ...... The number of paths traced: 2477. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 35704 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 8856 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__216 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 234 # Stopped at ebeam_ctrl_tbw.ant line 234 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12312 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__298 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 316 # Stopped at ebeam_ctrl_tbw.ant line 316 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12312 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__298 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 316 # Stopped at ebeam_ctrl_tbw.ant line 316 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12312 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__298 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 316 # Stopped at ebeam_ctrl_tbw.ant line 316 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 23. Undefined symbol 'ebeam_data'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 23. ebeam_data: Undefined symbol (last report in this block) ERROR:HDLParsers:507 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 22. ) is not a correct resolution function name ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 23. parse error, unexpected COLON, expecting SEMICOLON or CLOSEPAR ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12312 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__318 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 336 # Stopped at ebeam_ctrl_tbw.ant line 336 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading c:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading c:/Modeltech_xe/win32xoem/../std.standard # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading c:/Modeltech_xe/win32xoem/../std.textio(body) # Loading c:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12312 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__321 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 339 # Stopped at ebeam_ctrl_tbw.ant line 339 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 2408 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__168 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 182 # Stopped at ebeam_ctrl_tbw.ant line 182 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 36008 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 227 # Stopped at ebeam_ctrl_tbw.ant line 227 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks............................................................................................................................................................................ Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 36008 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 227 # Stopped at ebeam_ctrl_tbw.ant line 227 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 36008 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 227 # Stopped at ebeam_ctrl_tbw.ant line 227 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. 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__projnav/ebeam.gfl deleting __projnav/ebeam_flowplus.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 36008 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 227 # Stopped at ebeam_ctrl_tbw.ant line 227 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 31200 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 223 # Stopped at ebeam_ctrl_tbw.ant line 223 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62400 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__210 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 232 # Stopped at ebeam_ctrl_tbw.ant line 232 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62400 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__210 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 235 # Stopped at ebeam_ctrl_tbw.ant line 235 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1348. ....... The number of paths traced: 2697. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62400 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__210 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 235 # Stopped at ebeam_ctrl_tbw.ant line 235 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62400 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__207 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 232 # Stopped at ebeam_ctrl_tbw.ant line 232 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62410 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__210 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 235 # Stopped at ebeam_ctrl_tbw.ant line 235 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62410 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__216 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 241 # Stopped at ebeam_ctrl_tbw.ant line 241 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1348. ....... The number of paths traced: 2697. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__88 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 111 # Stopped at ebeamux_tbw.ant line 111 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__88 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 109 # Stopped at ebeamux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 42. parse error, unexpected TOKOUT WARNING:HDLParsers:901 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Line 42. Label mux is ignored. --> Total memory usage is 44624 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd line 35: The following signals are missing in the process sensitivity list: muxsel. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeammux.ngc ebeammux.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 33504 kilobytes Writing NGD file "ebeammux.ngd" ... Writing NGDBUILD log file "ebeammux.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 16 equations into 16 function blocks................................................. Design ebeammux has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 128. . The number of paths traced: 257. Generating performance summary ... ebeammux.tim has been created. Generating Stamp model files ebeammux.mod, ebeammux.data ... ebeammux.mod has been created. ebeammux.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd line 35: The following signals are missing in the process sensitivity list: muxsel. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeammux.ngc ebeammux.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 33504 kilobytes Writing NGD file "ebeammux.ngd" ... Writing NGDBUILD log file "ebeammux.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 16 equations into 16 function blocks................................................. Design ebeammux has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 128. . The number of paths traced: 257. Generating performance summary ... ebeammux.tim has been created. Generating Stamp model files ebeammux.mod, ebeammux.data ... ebeammux.mod has been created. ebeammux.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__88 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 109 # Stopped at ebeamux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62410 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__211 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 236 # Stopped at ebeam_ctrl_tbw.ant line 236 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62410 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__211 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 236 # Stopped at ebeam_ctrl_tbw.ant line 236 Project Navigator Auto-Make Log File ------------------------------------- WARNING:HDLParsers:3215 - Unit work/EBEAMMUX is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd, now is E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd WARNING:HDLParsers:3215 - Unit work/EBEAMMUX/BEHAVIORAL is now defined in a different file: was C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd, now is E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd Compiling vhdl file E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__88 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 109 # Stopped at ebeamux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__88 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 109 # Stopped at ebeamux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do ebeamux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamux_tbw # -- Compiling architecture testbench_arch of ebeamux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeamux_tbw # -- Loading architecture testbench_arch of ebeamux_tbw # vsim -lib work -t 1ps ebeamux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 12 ns Iteration: 0 Process: /ebeamux_tbw/line__73 File: ebeamux_tbw.ant # Break at ebeamux_tbw.ant line 89 # Stopped at ebeamux_tbw.ant line 89 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 15 ns Iteration: 0 Process: /mux_tbw/line__73 File: mux_tbw.ant # Break at mux_tbw.ant line 89 # Stopped at mux_tbw.ant line 89 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__73 File: mux_tbw.ant # Break at mux_tbw.ant line 89 # Stopped at mux_tbw.ant line 89 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__73 File: mux_tbw.ant # Break at mux_tbw.ant line 92 # Stopped at mux_tbw.ant line 92 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__79 File: mux_tbw.ant # Break at mux_tbw.ant line 99 # Stopped at mux_tbw.ant line 99 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__79 File: mux_tbw.ant # Break at mux_tbw.ant line 103 # Stopped at mux_tbw.ant line 103 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl # 5.7c # do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe_starter/win32xoem/../std.standard # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe_starter/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe_starter/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__79 File: mux_tbw.ant # Break at mux_tbw.ant line 109 # Stopped at mux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # ** Error: (vsim-7) Failed to open VHDL file "e:\xilinx\work\ebeam\ebeam\mux_tbw.ano" in r+ mode. # No such file or directory. (errno = ENOENT) # Time: 0 ps Iteration: 0 Region: /mux_tbw File: mux_tbw.ant # Loading work.ebeammux(behavioral) # ** Fatal: (vsim-7) Failed to open VHDL file "e:\xilinx\work\ebeam\ebeam\mux_tbw.ano" in r+ mode. # No such file or directory. (errno = ENOENT) # Time: 5 ns Iteration: 0 Process: /mux_tbw/line__50 File: mux_tbw.ant # Fatal error at mux_tbw.ant line 64 # # Stopped at mux_tbw.ant line 64 # Executing ONERROR command at macro ./mux_tbw.ado line 13 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # ** Error: (vsim-7) Failed to open VHDL file "e:\xilinx\work\ebeam\ebeam\mux_tbw.ano" in r+ mode. # No such file or directory. (errno = ENOENT) # Time: 0 ps Iteration: 0 Region: /mux_tbw File: mux_tbw.ant # Loading work.ebeammux(behavioral) # ** Fatal: (vsim-7) Failed to open VHDL file "e:\xilinx\work\ebeam\ebeam\mux_tbw.ano" in r+ mode. # No such file or directory. (errno = ENOENT) # Time: 5 ns Iteration: 0 Process: /mux_tbw/line__50 File: mux_tbw.ant # Fatal error at mux_tbw.ant line 64 # # Stopped at mux_tbw.ant line 64 # Executing ONERROR command at macro ./mux_tbw.ado line 13 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__79 File: mux_tbw.ant # Break at mux_tbw.ant line 109 # Stopped at mux_tbw.ant line 109 Project Navigator Auto-Make Log File ------------------------------------- WARNING:HDLParsers:3215 - Unit work/EBEAMMUX is now defined in a different file: was E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd, now is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd WARNING:HDLParsers:3215 - Unit work/EBEAMMUX/BEHAVIORAL is now defined in a different file: was E:/Xilinx/Work/Ebeam/ebeam/ebeammux.vhd, now is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 190 ns Iteration: 0 Process: /mux_tbw/line__88 File: mux_tbw.ant # Break at mux_tbw.ant line 119 # Stopped at mux_tbw.ant line 119 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do mux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity mux_tbw # -- Compiling architecture testbench_arch of mux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity mux_tbw # -- Loading architecture testbench_arch of mux_tbw # vsim -lib work -t 1ps mux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.mux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 355 ns Iteration: 0 Process: /mux_tbw/line__88 File: mux_tbw.ant # Break at mux_tbw.ant line 145 # Stopped at mux_tbw.ant line 145 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_ctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_ctrl_tbw # -- Compiling architecture testbench_arch of ebeam_ctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_ctrl_tbw # -- Loading architecture testbench_arch of ebeam_ctrl_tbw # vsim -lib work -t 1ps ebeam_ctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_ctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 62410 ns Iteration: 0 Process: /ebeam_ctrl_tbw/line__211 File: ebeam_ctrl_tbw.ant # Break at ebeam_ctrl_tbw.ant line 236 # Stopped at ebeam_ctrl_tbw.ant line 236 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 11 16-bit register : 10 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 4808 ns Iteration: 0 Process: /ebeammux_tbw/line__101 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 126 # Stopped at ebeammux_tbw.ant line 126 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 4808 ns Iteration: 0 Process: /ebeammux_tbw/line__101 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 126 # Stopped at ebeammux_tbw.ant line 126 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 4808 ns Iteration: 0 Process: /ebeammux_tbw/line__101 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 126 # Stopped at ebeammux_tbw.ant line 126 Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__101 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 162 # Stopped at ebeammux_tbw.ant line 162 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). ERROR:Xst:827 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd line 32: Signal muxout cannot be synthesized, bad synchronous description. --> Total memory usage is 45648 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). ERROR:Xst:827 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd line 32: Signal muxout cannot be synthesized, bad synchronous description. --> Total memory usage is 45648 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1348 - Unit ebeammux is merged (output interface has tristates) WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND ERROR:Xst:415 - Synthesis failed CPU : 0.69 / 0.98 s | Elapsed : 0.00 / 0.00 s --> Total memory usage is 49744 kilobytes Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1348 - Unit ebeammux is merged (output interface has tristates) WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND ERROR:Xst:415 - Synthesis failed CPU : 0.72 / 1.01 s | Elapsed : 1.00 / 1.00 s --> Total memory usage is 49744 kilobytes Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1348. ....... The number of paths traced: 2697. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1348 - Unit ebeammux is merged (output interface has tristates) WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND ERROR:Xst:415 - Synthesis failed CPU : 0.74 / 1.03 s | Elapsed : 1.00 / 1.00 s --> Total memory usage is 49744 kilobytes Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1348. ....... The number of paths traced: 2697. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1348 - Unit ebeammux is merged (output interface has tristates) WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND WARNING:Xst:528 - Multi-source in Unit on signal not replaced by logic Signal is stuck at GND ERROR:Xst:415 - Synthesis failed CPU : 0.70 / 1.00 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 49744 kilobytes Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks.............................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Project Navigator Auto-Make Log File ------------------------------------- deleting ebeam_ctrl_tbw.ado deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl.lso deleting ebeam_ctrl.syr deleting ebeam_ctrl.prj deleting ebeam_ctrl.sprj deleting ebeam_ctrl.ana deleting ebeam_ctrl.stx deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl.ngc deleting ebeam_ctrl.ngr deleting __projnav/ebeam_ctrl_edfTOngd_tcl.rsp deleting ebeam_ctrl.ngd deleting ebeam_ctrl.bld deleting ebeam_ctrl_ngdbuild.nav deleting _ngo/netlist.lst deleting .untf deleting ebeam_ctrl_html deleting ebeam_ctrl.cmd_log deleting __projnav/ebeam_ctrl_ngdTOvm6_tcl.rsp deleting ebeam_ctrl.vm6 deleting ebeam_ctrl.cxt deleting ebeam_ctrl.blx deleting ebeam_ctrl.mfd deleting ebeam_ctrl.rpt deleting ebeam_ctrl.log deleting ebeam_ctrl.pnx deleting ebeam_ctrl.gyd deleting ebeam_ctrl.xml deleting ebeam_ctrl_build.xml deleting ebeam.ptf deleting ebeam_ctrl.bl deleting errors.xml deleting tmperr.err deleting ebeam_ctrl.cmd_log deleting __projnav/ebeam_ctrl_vm6TOnga_tcl.rsp deleting ebeam_ctrl.nga deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl_timesim.vhd deleting ebeam_ctrl_timesim.vhd deleting ngaTOebeam_ctrl.vhdsim_par deleting ebeam_ctrl.vhdsim_par deleting ebeam_ctrl_timesim.nlf deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl_tbw.timesim_vhw deleting _remap.tmp deleting __projnav/ptb.rsp deleting ebeam_ctrl_tbw.tdo deleting vsim.wlf deleting C:\jfb\Xilinx\MWD\Work\Ebeam\ebeam\__projnav\hb_cmds deleting ebeam_ctrl_tbw.ado deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.ado deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.ado deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.timesim_vhw deleting _remap.tmp deleting __projnav/ptb.rsp deleting ebeam_ctrl_tbw.tdo deleting vsim.wlf deleting __projnav/updateTBW_tcl.rsp deleting ebeam_ctrl_tbw.vhw deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.tfw deleting ebeam_ctrl_tbw.fdo deleting vsim.wlf deleting ebeam_ctrl_tbw.timesim_vhw deleting _remap.tmp deleting __projnav/ptb.rsp deleting ebeam_ctrl_tbw.tdo deleting vsim.wlf deleting ebeam_ctrl.syr deleting ebeam_ctrl.prj deleting ebeam_ctrl.sprj deleting ebeam_ctrl.ana deleting ebeam_ctrl.stx deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl.ngc deleting ebeam_ctrl.ngr deleting __projnav/ebeam_ctrl_edfTOngd_tcl.rsp deleting ebeam_ctrl.ngd deleting ebeam_ctrl.bld deleting ebeam_ctrl_ngdbuild.nav deleting _ngo/netlist.lst deleting .untf deleting ebeam_ctrl_html deleting ebeam_ctrl.cmd_log deleting __projnav/ebeam_ctrl_ngdTOvm6_tcl.rsp deleting ebeam_ctrl.vm6 deleting ebeam_ctrl.cxt deleting ebeam_ctrl.blx deleting ebeam_ctrl.mfd deleting ebeam_ctrl.rpt deleting ebeam_ctrl.log deleting ebeam_ctrl.pnx deleting ebeam_ctrl.gyd deleting ebeam_ctrl.xml deleting ebeam_ctrl_build.xml deleting ebeam.ptf deleting ebeam_ctrl.bl deleting errors.xml deleting tmperr.err deleting ebeam_ctrl.cmd_log deleting __projnav/ebeam_ctrl_vm6TOjed_tcl.rsp deleting ebeam_ctrl.jed deleting ebeam_ctrl.isc deleting ebeam_ctrl.cmd_log deleting __projnav/ebeam_ctrl_vm6TOtim_tcl.rsp deleting ebeam_ctrl.tim deleting ebeam_ctrl.mod deleting ebeam_ctrl.data deleting ebeam_ctrl.cmd_log deleting c:\jfb\xilinx\mwd\work\ebeam\ebeam/ebeam_ctrl_html deleting __projnav\taengine.err deleting ebeam_ctrl_html deleting ebeam_ctrl._hrpt deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl.imp deleting __projnav/ebeam_ctrl_vm6TOnga_tcl.rsp deleting ebeam_ctrl.nga deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl_timesim.vhd deleting ebeam_ctrl_timesim.vhd deleting ngaTOebeam_ctrl.vhdsim_par deleting ebeam_ctrl.vhdsim_par deleting ebeam_ctrl_timesim.nlf deleting ebeam_ctrl.cmd_log deleting ebeam_ctrl_tbw.timesim_vhw deleting _remap.tmp deleting __projnav/ptb.rsp deleting ebeam_ctrl_tbw.tdo deleting vsim.wlf deleting __projnav/updateTBW_tcl.rsp deleting ebeam_ctrl_tbw.vhw deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.tfw deleting ebeam_ctrl_tbw.ado deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.ado deleting 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ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeammux.prj deleting ebeammux.prj deleting __projnav/ebeammux.xst deleting ./xst deleting ebeammux.prj deleting ebeammux.prj deleting __projnav/ebeammux.xst deleting ./xst deleting ebeammux.prj deleting ebeammux.prj deleting __projnav/ebeammux.xst deleting ./xst deleting ebeammux.prj deleting ebeammux.prj deleting __projnav/ebeammux.xst deleting ./xst deleting ebeam_ctrl.prj deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting ebeam_ctrl.prj deleting __projnav/ebeam_ctrl.xst deleting ./xst deleting __projnav/ebeam.gfl deleting __projnav/ebeam_flowplus.gfl Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__104 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 166 # Stopped at ebeammux_tbw.ant line 166 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__104 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 166 # Stopped at ebeammux_tbw.ant line 166 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__104 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 166 # Stopped at ebeammux_tbw.ant line 166 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__104 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 167 # Stopped at ebeammux_tbw.ant line 167 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeammux_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeammux_tbw # -- Compiling architecture testbench_arch of ebeammux_tbw # -- Loading entity ebeammux # -- Compiling configuration ebeammux_cfg # -- Loading entity ebeammux_tbw # -- Loading architecture testbench_arch of ebeammux_tbw # vsim -lib work -t 1ps ebeammux_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeammux_tbw(testbench_arch) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 91208 ns Iteration: 0 Process: /ebeammux_tbw/line__101 File: ebeammux_tbw.ant # Break at ebeammux_tbw.ant line 162 # Stopped at ebeammux_tbw.ant line 162 Project Navigator Auto-Make Log File ------------------------------------- ERROR: Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 48008 ns Iteration: 0 Process: /ebeamctrl_tbw/line__216 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 232 # Stopped at ebeamctrl_tbw.ant line 232 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ........... The number of paths traced: 1396. ....... The number of paths traced: 2793. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 48008 ns Iteration: 0 Process: /ebeamctrl_tbw/line__216 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 238 # Stopped at ebeamctrl_tbw.ant line 238 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch # -- Compiling architecture behavioral of timelatch # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity dff # -- Loading entity timelatch # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 84004 ns Iteration: 0 Process: /ebeamctrl_tbw/line__255 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 277 # Stopped at ebeamctrl_tbw.ant line 277 Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "View RTL Schematic". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Completed process "View RTL Schematic". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd Line 57. parse error, unexpected IF, expecting PROCESS --> Total memory usage is 44624 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks......................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Architecture behavioral of Entity timelatch is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks........................................................................................ Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 12 16-bit register : 11 1-bit register : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization................ Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 179 equations into 16 function blocks........................................................................................ Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1413. ....... The number of paths traced: 2827. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock ebeam_sync.Q ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do edge_en_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # ** Error: edge_en.vhd(53): Unknown identifier: clk # ** Error: edge_en.vhd(53): Expression is not a signal. # ** Error: edge_en.vhd(59): Unknown identifier: clk # ** Error: edge_en.vhd(59): Attribute event requires a static signal prefix. # ** Error: edge_en.vhd(59): Unknown identifier: clk # ** Error: edge_en.vhd(59): Bad expression. # ** Error: edge_en.vhd(59): Type error resolving infix expression. # ** Error: edge_en.vhd(69): near ")": expecting: STRING IDENTIFIER # ** Error: edge_en.vhd(128): near "process": expecting: ';' # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./edge_en_tbw.ado line 11 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. ERROR:HDLParsers:3312 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd Line 53. Undefined symbol 'clk'. ERROR:HDLParsers:1209 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd Line 53. clk: Undefined symbol (last report in this block) ERROR:HDLParsers:808 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd Line 59. = can not have such operands in this context. ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd Line 69. parse error, unexpected CLOSEPAR, expecting IDENTIFIER or STRING_LITERAL ERROR:HDLParsers:164 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd Line 78. parse error, unexpected IF --> Total memory usage is 44624 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 1 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 1 1-bit register : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl edge_en.ngc edge_en.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 33504 kilobytes Writing NGD file "edge_en.ngd" ... Writing NGDBUILD log file "edge_en.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 5 equations into 16 function blocks............... Design edge_en has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 12. The number of paths traced: 25. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock timeclk ... edge_en.tim has been created. Generating Stamp model files edge_en.mod, edge_en.data ... edge_en.mod has been created. edge_en.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 1 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 1 1-bit register : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl edge_en.ngc edge_en.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 33504 kilobytes Writing NGD file "edge_en.ngd" ... Writing NGDBUILD log file "edge_en.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Timing optimization Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 5 equations into 16 function blocks............... Design edge_en has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ..... The number of paths traced: 12. The number of paths traced: 25. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock timeclk ... edge_en.tim has been created. Generating Stamp model files edge_en.mod, edge_en.data ... edge_en.mod has been created. edge_en.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do edge_en_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity edge_en_tbw # -- Compiling architecture testbench_arch of edge_en_tbw # -- Loading entity edge_en # -- Compiling configuration edge_en_cfg # -- Loading entity edge_en_tbw # -- Loading architecture testbench_arch of edge_en_tbw # vsim -lib work -t 1ps edge_en_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.edge_en_tbw(testbench_arch) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 4088 ns Iteration: 0 Process: /edge_en_tbw/line__100 File: edge_en_tbw.ant # Break at edge_en_tbw.ant line 124 # Stopped at edge_en_tbw.ant line 124 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do edge_en_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity edge_en_tbw # -- Compiling architecture testbench_arch of edge_en_tbw # -- Loading entity edge_en # -- Compiling configuration edge_en_cfg # -- Loading entity edge_en_tbw # -- Loading architecture testbench_arch of edge_en_tbw # vsim -lib work -t 1ps edge_en_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.edge_en_tbw(testbench_arch) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 4088 ns Iteration: 0 Process: /edge_en_tbw/line__100 File: edge_en_tbw.ant # Break at edge_en_tbw.ant line 124 # Stopped at edge_en_tbw.ant line 124 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Instantiation Template". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Completed process "View VHDL Instantiation Template". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. WARNING:Xst:1780 - Signal is never used or assigned. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 12 1-bit register : 1 16-bit register : 11 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 12 1-bit register : 1 16-bit register : 11 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks..................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1503. ........ The number of paths traced: 3007. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 84004 ns Iteration: 0 Process: /ebeamctrl_tbw/line__235 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 257 # Stopped at ebeamctrl_tbw.ant line 257 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 84004 ns Iteration: 0 Process: /ebeamctrl_tbw/line__235 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 257 # Stopped at ebeamctrl_tbw.ant line 257 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # ** Error: ebeam_ctrl.vhd(117): Illegal target for signal assignment. # ** Error: ebeam_ctrl.vhd(118): No feasible entries for infix op: "and" # ** Error: ebeam_ctrl.vhd(117): Unknown identifier: toto # ** Error: ebeam_ctrl.vhd(118): Target of signal assignment is not a signal. # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # WARNING[1]: ebeam_ctrl.vhd(189): No default binding for component: "ebeammux". (Port "toto" is not on the entity) # ** Error: ebeam_ctrl.vhd(192): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./ebeamctrl_tbw.ado line 15 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:3313 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 117. Undefined symbol 'toto'. Should it be: 'to to'? ERROR:HDLParsers:808 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 118. and can not have such operands in this context. --> Total memory usage is 44624 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:3313 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 117. Undefined symbol 'toto'. Should it be: 'to to'? --> Total memory usage is 44624 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 12 1-bit register : 1 16-bit register : 11 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks.................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1535. ........ The number of paths traced: 3071. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 84004 ns Iteration: 0 Process: /ebeamctrl_tbw/line__255 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 268 # Stopped at ebeamctrl_tbw.ant line 268 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeamctrl_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeamctrl_tbw # -- Compiling architecture testbench_arch of ebeamctrl_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeamctrl_tbw # -- Loading architecture testbench_arch of ebeamctrl_tbw # vsim -lib work -t 1ps ebeamctrl_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeamctrl_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 84004 ns Iteration: 0 Process: /ebeamctrl_tbw/line__209 File: ebeamctrl_tbw.ant # Break at ebeamctrl_tbw.ant line 222 # Stopped at ebeamctrl_tbw.ant line 222 Project Navigator Auto-Make Log File ------------------------------------- deleting __projnav/updateTBW_tcl.rsp deleting ebeammux_tbw.vhw deleting ebeammux_tbw.ano deleting ebeammux_tbw.tfw deleting ebeammux_tbw.ado deleting ebeammux_tbw.ano deleting ebeammux_tbw.ado deleting ebeammux_tbw.ano deleting ebeammux_tbw.ado deleting ebeammux_tbw.ano deleting ebeammux_tbw.ado deleting ebeammux_tbw.ano deleting __projnav/updateTBW_tcl.rsp deleting ebeammux_tbw.vhw deleting ebeammux_tbw.ano deleting ebeammux_tbw.tfw deleting ebeammux_tbw.ado deleting ebeammux_tbw.ano deleting __projnav/updateTBW_tcl.rsp deleting ebeam_ctrl_tbw.vhw deleting ebeam_ctrl_tbw.ano deleting ebeam_ctrl_tbw.tfw deleting C:\jfb\Xilinx\MWD\Work\Ebeam\ebeam\__projnav\hb_cmds deleting ebeamctrl_tbw.ado deleting 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__projnav/p007u000.kis deleting __projnav/p00hi000.kis Finished cleaning up project Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 49928 ns Iteration: 0 Process: /ebeam_tbw/line__207 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 220 # Stopped at ebeam_tbw.ant line 220 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__210 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 223 # Stopped at ebeam_tbw.ant line 223 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__230 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 243 # Stopped at ebeam_tbw.ant line 243 Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. ERROR:HDLParsers:1402 - C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd Line 118. Object tutu of mode IN can not be updated. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # ** Error: ebeam_ctrl.vhd(118): Cannot drive input signal: tutu. # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # ** Error: ebeam_ctrl.vhd(194): VHDL Compiler exiting # ERROR: can't read "PrefDefault(MouseButtons)": no such element in array # Initialization problem, exiting. # # Initialization problem, exiting. # Executing ONERROR command at macro ./ebeam_tbw.ado line 15 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__230 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 243 # Stopped at ebeam_tbw.ant line 243 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__250 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 263 # Stopped at ebeam_tbw.ant line 263 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__250 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 263 # Stopped at ebeam_tbw.ant line 263 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. WARNING:Xst:737 - Found 16-bit latch for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 11 1-bit register : 1 16-bit register : 10 # Latches : 1 16-bit latch : 1 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 182 equations into 16 function blocks............................................................................................ Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 11 1-bit register : 1 16-bit register : 10 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................... Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 182 equations into 16 function blocks................................................................................................. Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... ERROR:NgdBuild:755 - Line 11 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<16>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 12 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<17>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 24 in 'ebeam_ctrl.ucf': Could not find net(s) 'lower' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 31 in 'ebeam_ctrl.ucf': Could not find net(s) 'upper' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "ebeam_ctrl.ucf". Writing NGDBUILD log file "ebeam_ctrl.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... ERROR:NgdBuild:755 - Line 11 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<16>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 12 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<17>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 24 in 'ebeam_ctrl.ucf': Could not find net(s) 'lower' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 31 in 'ebeam_ctrl.ucf': Could not find net(s) 'upper' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "ebeam_ctrl.ucf". Writing NGDBUILD log file "ebeam_ctrl.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... ERROR:NgdBuild:755 - Line 11 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<16>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 12 in 'ebeam_ctrl.ucf': Could not find net(s) 'ebeam_data<17>' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 24 in 'ebeam_ctrl.ucf': Could not find net(s) 'lower' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:NgdBuild:755 - Line 31 in 'ebeam_ctrl.ucf': Could not find net(s) 'upper' in the design. To suppress this error specify the correct net name or remove the constraint. The 'Ignore I\O constraints on Invalid Object Names' property can also be set ( -aul switch for command line users). ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "ebeam_ctrl.ucf". Writing NGDBUILD log file "ebeam_ctrl.bld"... Error: Process "Translate" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -i -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Architecture behavioral of Entity counter32 is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 11 1-bit register : 1 16-bit register : 10 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 34528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks................................................................................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1453. ....... The number of paths traced: 2907. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.Reading C:/Modeltech_xe/tcl/vsim/pref.tcl # 5.7c # ** Warning: A ModelSim starter license was detected and will be used, even though you have installed ModelSim XE. You should obtain an XE license in order to access ModelSim XE's full capabilities.do ebeam_tbw.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity counter32 # -- Compiling architecture behavioral of counter32 # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity dff # -- Compiling architecture behavioral of dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity edge_en # -- Compiling architecture behavioral of edge_en # -- Loading entity dff # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity timelatch_en # -- Compiling architecture behavioral of timelatch_en # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeammux # -- Compiling architecture behavioral of ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity ebeam_ctrl # -- Compiling architecture behavioral of ebeam_ctrl # -- Loading entity counter32 # -- Loading entity edge_en # -- Loading entity timelatch_en # -- Loading entity ebeammux # Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity ebeam_tbw # -- Compiling architecture testbench_arch of ebeam_tbw # -- Loading entity ebeam_ctrl # -- Compiling configuration ebeam_ctrl_cfg # -- Loading entity ebeam_tbw # -- Loading architecture testbench_arch of ebeam_tbw # vsim -lib work -t 1ps ebeam_tbw # Loading C:/Modeltech_xe/win32xoem/../std.standard # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_1164(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_arith(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_unsigned(body) # Loading C:/Modeltech_xe/win32xoem/../std.textio(body) # Loading C:/Modeltech_xe/win32xoem/../ieee.std_logic_textio(body) # Loading work.ebeam_tbw(testbench_arch) # Loading work.ebeam_ctrl(behavioral) # Loading work.counter32(behavioral) # Loading work.edge_en(behavioral) # Loading work.dff(behavioral) # Loading work.timelatch_en(behavioral) # Loading work.ebeammux(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 57608 ns Iteration: 0 Process: /ebeam_tbw/line__190 File: ebeam_tbw.ant # Break at ebeam_tbw.ant line 212 # Stopped at ebeam_tbw.ant line 212 Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37900 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35552 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-6-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks..................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-6-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1453. ....... The number of paths traced: 2907. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Fit Simulation Model". Release 6.1.03i - CPLD Timing Simulation Interface G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Creating NGA for simulation. Speed File: Version 3.0 Completed process "Generate Post-Fit Simulation Model". Release 6.1.03i - netgen G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Reading design ebeam_ctrl.nga ... Flattening design ... Flattening design completed. Specializing design ... Specializing design completed. Preping physical only global signals ... Preping design's networks ... Preping design's macros ... Writing VHDL netlist ebeam_ctrl_timesim.vhd ... Writing VHDL SDF file ebeam_ctrl_timesim.sdf ... Total memory usage is 37876 kilobytes Created netgen log file 'ebeam_ctrl_timesim.nlf'. Completed process "Generate Post-Fit Simulation Model". Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-7-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization.............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 181 equations into 16 function blocks..................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-7-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1453. ....... The number of paths traced: 2907. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd in Library work. Architecture behavioral of Entity dff is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd in Library work. Architecture behavioral of Entity edge_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd in Library work. Architecture behavioral of Entity timelatch_en is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd in Library work. Architecture behavioral of Entity ebeammux is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd in Library work. Architecture behavioral of Entity ebeam_ctrl is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011" for signal . Set property "ENUM_ENCODING = 000 001 010 011" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/dff.vhd. Found 1-bit register for signal . Summary: inferred 1 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeammux.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/timelatch_en.vhd. Found 16-bit register for signal . Found 16-bit register for signal . Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/edge_en.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 1 | | Outputs | 2 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Summary: inferred 1 Finite State Machine(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/counter32.vhd. Found 16-bit comparator less for signal <$n0005> created at line 52. Found 16-bit comparator less for signal <$n0006> created at line 59. Found 16-bit adder for signal <$n0007> created at line 53. Found 16-bit adder for signal <$n0008> created at line 60. Found 16-bit register for signal . Found 16-bit register for signal . Summary: inferred 2 Adder/Subtracter(s). inferred 2 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.vhd. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 11 1-bit register : 1 16-bit register : 10 # Adders/Subtractors : 2 16-bit adder : 2 # Comparators : 2 16-bit comparator less : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Sequential flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... implementation constraint: INIT=r : cnt1_13 implementation constraint: INIT=r : cnt2_13 implementation constraint: INIT=r : cnt1_11 implementation constraint: INIT=r : cnt1_12 implementation constraint: INIT=r : cnt2_15 implementation constraint: INIT=r : cnt2_14 implementation constraint: INIT=r : cnt2_0 implementation constraint: INIT=r : cnt2_1 implementation constraint: INIT=r : cnt2_2 implementation constraint: INIT=r : cnt2_3 implementation constraint: INIT=r : cnt2_4 implementation constraint: INIT=r : cnt2_5 implementation constraint: INIT=r : cnt2_6 implementation constraint: INIT=r : cnt2_7 implementation constraint: INIT=r : cnt2_8 implementation constraint: INIT=r : cnt2_9 implementation constraint: INIT=r : cnt2_10 implementation constraint: INIT=r : cnt2_11 implementation constraint: INIT=r : cnt2_12 implementation constraint: INIT=r : cnt1_15 implementation constraint: INIT=r : cnt1_14 implementation constraint: INIT=r : cnt1_0 implementation constraint: INIT=r : cnt1_1 implementation constraint: INIT=r : cnt1_2 implementation constraint: INIT=r : cnt1_3 implementation constraint: INIT=r : cnt1_4 implementation constraint: INIT=r : cnt1_5 implementation constraint: INIT=r : cnt1_6 implementation constraint: INIT=r : cnt1_7 implementation constraint: INIT=r : cnt1_8 implementation constraint: INIT=r : cnt1_9 implementation constraint: INIT=r : cnt1_10 Optimizing unit ... Optimizing unit ... Completed process "Synthesize". Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-7-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 180 equations into 16 function blocks..................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-7-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1533. ........ The number of paths traced: 3067. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-7-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 180 equations into 16 function blocks..................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-7-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1533. ........ The number of paths traced: 3067. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Release 6.1.03i - ngdbuild G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Command Line: ngdbuild -dd _ngo -uc ebeam_ctrl.ucf -p xc9500xl ebeam_ctrl.ngc ebeam_ctrl.ngd Reading NGO file "C:/jfb/Xilinx/MWD/Work/Ebeam/ebeam/ebeam_ctrl.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ebeam_ctrl.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 35528 kilobytes Writing NGD file "ebeam_ctrl.ngd" ... Writing NGDBUILD log file "ebeam_ctrl.bld"... NGDBUILD done. Completed process "Translate". Started process "Fit". Release 6.1.03i - CPLD Optimizer/Partitioner G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Considering device XC95288XL-7-TQ144. Flattening design.. Multi-level logic optimization... Timing optimization............................................................................. Timing driven global resource optimization General global resource optimization........ Re-checking device resources ... Mapping a total of 180 equations into 16 function blocks..................... Design ebeam_ctrl has been optimized and fit into device XC95288XL-7-TQ144. Completed process "Fit". Started process "Generate Programming File". Release 6.1.03i - Programming File Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Completed process "Generate Programming File". Started process "Generate Timing". Release 6.1.03i - Timing Report Generator G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. Path tracing ............ The number of paths traced: 1533. ........ The number of paths traced: 3067. Generating performance summary ... Generating Pad-to-Pad delay section ... Generating Clock-to-Output-Pad delay section ... Generating Setup-To-Clock-At-Pad delay section ... Generating Register-To-Register delay section ... Cycle time table for clock sysclk ... Cycle time table for clock timeclk ... ebeam_ctrl.tim has been created. Generating Stamp model files ebeam_ctrl.mod, ebeam_ctrl.data ... ebeam_ctrl.mod has been created. ebeam_ctrl.data has been created. Completed process "Generate Timing". Project Navigator Auto-Make Log File -------------------------------------