-- VHDL Instantiation Created from source file trigger_synch.vhd -- 08:36:26 02/27/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT trigger_synch
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		trigger_in : IN std_logic;
		trigger_en : IN std_logic;          
		trigger_out : OUT std_logic
		);
	END COMPONENT;

	Inst_trigger_synch: trigger_synch PORT MAP(
		reset => ,
		clk => ,
		trigger_in => ,
		trigger_en => ,
		trigger_out => 
	);