library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity trigger_synch is
    Port ( reset 			: in std_logic;
           clk 			: in std_logic;
           trigger_in 	: in std_logic;
           trigger_en 	: in std_logic;
           trigger_out	: out std_logic);
end trigger_synch;

architecture Behavioral of trigger_synch is

-- Components
	COMPONENT dffen
	PORT(
		reset : IN std_logic;
		clk 	: IN std_logic;
		en 	: IN std_logic;
		din 	: IN std_logic;          
		qout 	: OUT std_logic
		);
	END COMPONENT;

-- Signals
	signal trig_din : std_logic;
	signal trig_qout: std_logic;

begin

	trig_din <= not(trigger_en);

	Inst_dffen1: dffen PORT MAP(
		reset 	=> reset,
		clk 		=> trigger_in,
		en 		=> trigger_en,
		din 		=> trig_din,
		qout 		=> trig_qout
	);

	Inst_dffen2: dffen PORT MAP(
		reset 	=> reset,
		clk 		=> clk,
		en 		=> trigger_en,
		din 		=> trig_qout,
		qout 		=> trigger_out
	);





end Behavioral;