-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Mar 10 16:29:59 2004
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY trigger_sync_tbw IS
END trigger_sync_tbw;

ARCHITECTURE testbench_arch OF trigger_sync_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT trigger_synch
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			trigger_in : In  std_logic;
			trigger_en : In  std_logic;
			trigger_out : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL trigger_in : std_logic;
	SIGNAL trigger_en : std_logic;
	SIGNAL trigger_out : std_logic;

BEGIN
	UUT : trigger_synch
	PORT MAP (
		reset => reset,
		clk => clk,
		trigger_in => trigger_in,
		trigger_en => trigger_en,
		trigger_out => trigger_out
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		clk <= transport '1';
		WAIT FOR 6 ns;
		WAIT FOR 9 ns;
		clk <= transport '0';
		WAIT FOR 9 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_trigger_out(
			next_trigger_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (trigger_out /= next_trigger_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns trigger_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, trigger_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_trigger_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		reset <= transport '0';
		trigger_en <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=12 ns
		CHECK_trigger_out('0',12);
		-- --------------------
		WAIT FOR 18 ns; -- Time=30 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=42 ns
		CHECK_trigger_out('0',42);
		-- --------------------
		WAIT FOR 18 ns; -- Time=60 ns
		trigger_en <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=72 ns
		CHECK_trigger_out('0',72);
		-- --------------------
		WAIT FOR 30 ns; -- Time=102 ns
		CHECK_trigger_out('0',102);
		-- --------------------
		WAIT FOR 30 ns; -- Time=132 ns
		CHECK_trigger_out('0',132);
		-- --------------------
		WAIT FOR 30 ns; -- Time=162 ns
		CHECK_trigger_out('0',162);
		-- --------------------
		WAIT FOR 30 ns; -- Time=192 ns
		CHECK_trigger_out('1',192);
		-- --------------------
		WAIT FOR 30 ns; -- Time=222 ns
		CHECK_trigger_out('1',222);
		-- --------------------
		WAIT FOR 30 ns; -- Time=252 ns
		CHECK_trigger_out('1',252);
		-- --------------------
		WAIT FOR 30 ns; -- Time=282 ns
		CHECK_trigger_out('1',282);
		-- --------------------
		WAIT FOR 30 ns; -- Time=312 ns
		CHECK_trigger_out('1',312);
		-- --------------------
		WAIT FOR 18 ns; -- Time=330 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
	PROCESS   -- Process for Asynchronous Signals
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		BEGIN
		-- --------------------
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 48 ns; -- Time=48 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 60 ns; -- Time=108 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 48 ns; -- Time=156 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 28 ns; -- Time=184 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 44 ns; -- Time=228 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 56 ns; -- Time=284 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 46 ns; -- Time=330 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION trigger_synch_cfg OF trigger_sync_tbw IS
	FOR testbench_arch
	END FOR;
END trigger_synch_cfg;