version 3
trigger_synch.vhd
trigger_synch
VHDL
VHDL
trigger_sync_tbw.xwv
Clocked
-
-
1420000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
15000000
15000000
6000000
6000000
0
RISING
Asynchronous Signals
2000000
2000000
1000000
1000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
reset
clk
trigger_en
clk
trigger_out
clk
trigger_in
Asynchronous Signals
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
SIGNAL_ORDER_END
-X-X-X-
NOTE: This file was converted from the Granite version