-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Wed Mar 10 16:29:59 2004

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY trigger_sync_tbw IS
END trigger_sync_tbw;

ARCHITECTURE testbench_arch OF trigger_sync_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\channelctrl\chnctrl\trigger_sync_tbw.ano";
	COMPONENT trigger_synch
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			trigger_in : In  std_logic;
			trigger_en : In  std_logic;
			trigger_out : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL trigger_in : std_logic;
	SIGNAL trigger_en : std_logic;
	SIGNAL trigger_out : std_logic;

BEGIN
	UUT : trigger_synch
	PORT MAP (
		reset => reset,
		clk => clk,
		trigger_in => trigger_in,
		trigger_en => trigger_en,
		trigger_out => trigger_out
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_trigger_out(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",trigger_out,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, trigger_out);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		clk <= transport '1';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		ANNOTATE_trigger_out(TX_TIME);
		WAIT FOR 9 ns;
		TX_TIME := TX_TIME + 9;
		clk <= transport '0';
		WAIT FOR 9 ns;
		TX_TIME := TX_TIME + 9;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		trigger_en <= transport '1';
		-- --------------------
		WAIT FOR 30 ns; -- Time=30 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 30 ns; -- Time=60 ns
		trigger_en <= transport '0';
		-- --------------------
		WAIT FOR 270 ns; -- Time=330 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
	PROCESS   -- Process for Asynchronous Signals
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 48 ns; -- Time=48 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 60 ns; -- Time=108 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 48 ns; -- Time=156 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 28 ns; -- Time=184 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 44 ns; -- Time=228 ns
		trigger_in <= transport '1';
		-- --------------------
		WAIT FOR 56 ns; -- Time=284 ns
		trigger_in <= transport '0';
		-- --------------------
		WAIT FOR 46 ns; -- Time=330 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION trigger_synch_cfg OF trigger_sync_tbw IS
	FOR testbench_arch
	END FOR;
END trigger_synch_cfg;