# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do chn_ctrl_tb0.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity decim
# -- Compiling architecture behavioral of decim
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity ren_wen
# -- Compiling architecture behavioral of ren_wen
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity dffen
# -- Compiling architecture behavioral of dffen
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity trigger_synch
# -- Compiling architecture behavioral of trigger_synch
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity fsm1
# -- Compiling architecture behavioral of fsm1
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity chnctrl
# -- Compiling architecture behavioral of chnctrl
# Model Technology ModelSim XE III vcom 6.0a Compiler 2004.11 Nov 10 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity chn_ctrl_tb0
# -- Compiling architecture testbench_arch of chn_ctrl_tb0
# vsim -lib work -t 1ps chn_ctrl_tb0 
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading work.chn_ctrl_tb0(testbench_arch)
# Loading work.chnctrl(behavioral)
# Loading work.fsm1(behavioral)
# Loading work.ren_wen(behavioral)
# Loading work.decim(behavioral)
# Loading work.trigger_synch(behavioral)
# Loading work.dffen(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs
# .main_pane.workspace
# .main_pane.signals.interior.cs
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 10020 ns  Iteration: 0  Process: /chn_ctrl_tb0/line__123 File: chn_ctrl_tb0.vhw
# Break at chn_ctrl_tb0.vhw line 390
# Simulation Breakpoint: Break at chn_ctrl_tb0.vhw line 390
# MACRO ./chn_ctrl_tb0.fdo PAUSED at line 18
add wave sim:/chn_ctrl_tb0/uut/acqen_sig
add wave sim:/chn_ctrl_tb0/uut/trigger_en
add wave sim:/chn_ctrl_tb0/uut/trigger_out
add wave sim:/chn_ctrl_tb0/uut/reset_trig
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/reset
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/clk
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/acqen
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/trigmode
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/trigger
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/decim_ratio
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/ptrig_data
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/rstdataready
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/rst1
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/wen1
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/ren1
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/rst2
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/wen2
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/ren2
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/rst3
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/wen3
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/trigger_en
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/decim_flag
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/dataready
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/state
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/next_state
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/rst_fifo_cnt
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/enable_w2
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/enable_r2
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/decim_en
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/decim_flag_sig
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/wen2_sig
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/ren2_sig
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_delay_en
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_record_en
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_transfer_en
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_delay
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_record
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_transfer
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_delay_ovf
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_record_ptrg
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_record_ovf
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/cnt_transfer_ovf
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/ptrg_val_sig
add wave sim:/chn_ctrl_tb0/uut/inst_fsm1/dataready_sig
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/reset
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/clk
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/trigger_in
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/trigger_en
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/trigger_out
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/trig_din
add wave sim:/chn_ctrl_tb0/uut/inst_trigger_synch/trig_qout
restart
run -all
# ** Failure: Simulation successful (not a failure).  No problems detected.
#    Time: 10020 ns  Iteration: 0  Process: /chn_ctrl_tb0/line__123 File: chn_ctrl_tb0.vhw
# Break at chn_ctrl_tb0.vhw line 390