-- VHDL Test Bench Created from source file chnctrl.vhd -- 18:45:03 06/13/2006
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY chnctrl_testbench_vhd_tb IS
END chnctrl_testbench_vhd_tb;

ARCHITECTURE behavior OF chnctrl_testbench_vhd_tb IS 

	COMPONENT chnctrl
	PORT(
		reset 			: IN std_logic;
		clk 				: IN std_logic;
		trigmode 		: IN std_logic;
		decim_ratio 	: IN std_logic_vector(1 downto 0);
		ptrig_data 		: IN std_logic_vector(1 downto 0);
		acqen 			: IN std_logic;
		trigger 			: IN std_logic;
		rstdataready 	: IN std_logic;
		full3 			: IN std_logic;          
		rst1 				: OUT std_logic;
		wen1 				: OUT std_logic;
		ren1 				: OUT std_logic;
		rst2 				: OUT std_logic;
		wen2 				: OUT std_logic;
		ren2 				: OUT std_logic;
		rst3 				: OUT std_logic;
		wen3 				: OUT std_logic;
		latchtrig 		: OUT std_logic;
		dflag 			: OUT std_logic;
		dataready 		: OUT std_logic
		);
	END COMPONENT;

	-- inputs
	SIGNAL reset 			: std_logic := '0';
	SIGNAL clk 				: std_logic := '1';
	SIGNAL trigmode 		: std_logic	:=	'1';
	SIGNAL decim_ratio 	: std_logic_vector (1 DOWNTO 0):="11";
	SIGNAL ptrig_data 	: std_logic_vector (1 DOWNTO 0):="11";
	SIGNAL acqen 			: std_logic := '1';
	SIGNAL trigger 		: std_logic:='0';
	SIGNAL rstdataready 	: std_logic:='1';
	SIGNAL full3 			: std_logic:='1';
	
	-- outputs
	SIGNAL rst1 : std_logic;
	SIGNAL wen1 : std_logic;
	SIGNAL ren1 : std_logic;
	SIGNAL rst2 : std_logic;
	SIGNAL wen2 : std_logic;
	SIGNAL ren2 : std_logic;
	SIGNAL rst3 : std_logic;
	SIGNAL wen3 : std_logic;
	SIGNAL latchtrig : std_logic;
	SIGNAL dflag : std_logic;
	SIGNAL dataready : std_logic;

BEGIN
	UUT : chnctrl
	PORT MAP (
		reset 			=> reset,
		clk				=> clk,
		trigmode 		=> trigmode,
		decim_ratio 	=> decim_ratio,
		ptrig_data 		=> ptrig_data,
		acqen 			=> acqen,
		trigger 			=> trigger,
		rstdataready 	=> rstdataready,
		full3 			=> full3,
		rst1 				=> rst1,
		wen1 				=> wen1,
		ren1 				=> ren1,
		rst2 				=> rst2,
		wen2 				=> wen2,
		ren2 				=> ren2,
		rst3 				=> rst3,
		wen3 				=> wen3,
		latchtrig 		=> latchtrig,
		dflag 			=> dflag,
		dataready 		=> dataready
	);

		PROCESS    -- clock process for CLK_40MHZ
        BEGIN
            WAIT for 20 ns;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (20 ns);
                clk <= '1';
                WAIT FOR (20ns);
            END LOOP CLOCK_LOOP;
        END PROCESS;


	reset		<=	'0' after 0 ns;
	
	clk		<=	(not clk) after 50 ns;
	reset		<=	'1' after 300 ns;

	acqen		<=	'0' after 500 ns;

	trigger	<=	'1' after 2100 us,'0' after 2150 us;
	

end behavior;