-- E:\XILINX\CHANNELCTRL\CHNCTRL
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Jun 11 20:36:42 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ren_wen_tbw IS
END ren_wen_tbw;

ARCHITECTURE testbench_arch OF ren_wen_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT ren_wen
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			decim_ratio : In  std_logic_vector (1 DOWNTO 0);
			decim_en : In  std_logic;
			decim_flag : In  std_logic;
			enable_r : In  std_logic;
			enable_w : In  std_logic;
			wen2 : Out  std_logic;
			ren2 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL decim_ratio : std_logic_vector (1 DOWNTO 0);
	SIGNAL decim_en : std_logic;
	SIGNAL decim_flag : std_logic;
	SIGNAL enable_r : std_logic;
	SIGNAL enable_w : std_logic;
	SIGNAL wen2 : std_logic;
	SIGNAL ren2 : std_logic;

BEGIN
	UUT : ren_wen
	PORT MAP (
		reset => reset,
		clk => clk,
		decim_ratio => decim_ratio,
		decim_en => decim_en,
		decim_flag => decim_flag,
		enable_r => enable_r,
		enable_w => enable_w,
		wen2 => wen2,
		ren2 => ren2
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		clk <= transport '1';
		WAIT FOR 6 ns;
		WAIT FOR 44 ns;
		clk <= transport '0';
		WAIT FOR 44 ns;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_wen2(
			next_wen2 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (wen2 /= next_wen2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns wen2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wen2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_ren2(
			next_ren2 : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (ren2 /= next_ren2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns ren2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ren2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		reset <= transport '0';
		decim_ratio <= transport std_logic_vector'("01"); --1
		decim_en <= transport '1';
		decim_flag <= transport '0';
		enable_w <= transport '1';
		enable_r <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=12 ns
		CHECK_wen2('1',12);
		CHECK_ren2('1',12);
		-- --------------------
		WAIT FOR 100 ns; -- Time=112 ns
		CHECK_wen2('1',112);
		CHECK_ren2('1',112);
		-- --------------------
		WAIT FOR 88 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=212 ns
		CHECK_wen2('1',212);
		CHECK_ren2('1',212);
		-- --------------------
		WAIT FOR 100 ns; -- Time=312 ns
		CHECK_wen2('1',312);
		CHECK_ren2('1',312);
		-- --------------------
		WAIT FOR 88 ns; -- Time=400 ns
		decim_en <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=412 ns
		CHECK_wen2('1',412);
		CHECK_ren2('1',412);
		-- --------------------
		WAIT FOR 100 ns; -- Time=512 ns
		CHECK_wen2('1',512);
		CHECK_ren2('1',512);
		-- --------------------
		WAIT FOR 88 ns; -- Time=600 ns
		enable_w <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=612 ns
		CHECK_wen2('1',612);
		CHECK_ren2('1',612);
		-- --------------------
		WAIT FOR 100 ns; -- Time=712 ns
		CHECK_wen2('0',712);
		CHECK_ren2('1',712);
		-- --------------------
		WAIT FOR 100 ns; -- Time=812 ns
		CHECK_wen2('1',812);
		CHECK_ren2('1',812);
		-- --------------------
		WAIT FOR 100 ns; -- Time=912 ns
		CHECK_wen2('0',912);
		CHECK_ren2('1',912);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1012 ns
		CHECK_wen2('1',1012);
		CHECK_ren2('1',1012);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1112 ns
		CHECK_wen2('0',1112);
		CHECK_ren2('1',1112);
		-- --------------------
		WAIT FOR 88 ns; -- Time=1200 ns
		decim_flag <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=1212 ns
		CHECK_wen2('0',1212);
		CHECK_ren2('1',1212);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1312 ns
		CHECK_wen2('0',1312);
		CHECK_ren2('1',1312);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1412 ns
		CHECK_wen2('0',1412);
		CHECK_ren2('1',1412);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1512 ns
		CHECK_wen2('0',1512);
		CHECK_ren2('1',1512);
		-- --------------------
		WAIT FOR 88 ns; -- Time=1600 ns
		decim_flag <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=1612 ns
		CHECK_wen2('1',1612);
		CHECK_ren2('1',1612);
		-- --------------------
		WAIT FOR 88 ns; -- Time=1700 ns
		enable_r <= transport '0';
		-- --------------------
		WAIT FOR 12 ns; -- Time=1712 ns
		CHECK_wen2('0',1712);
		CHECK_ren2('0',1712);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1812 ns
		CHECK_wen2('1',1812);
		CHECK_ren2('1',1812);
		-- --------------------
		WAIT FOR 100 ns; -- Time=1912 ns
		CHECK_wen2('0',1912);
		CHECK_ren2('0',1912);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2012 ns
		CHECK_wen2('1',2012);
		CHECK_ren2('1',2012);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2112 ns
		CHECK_wen2('0',2112);
		CHECK_ren2('0',2112);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2212 ns
		CHECK_wen2('1',2212);
		CHECK_ren2('1',2212);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2312 ns
		CHECK_wen2('0',2312);
		CHECK_ren2('0',2312);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2412 ns
		CHECK_wen2('1',2412);
		CHECK_ren2('1',2412);
		-- --------------------
		WAIT FOR 88 ns; -- Time=2500 ns
		decim_flag <= transport '1';
		-- --------------------
		WAIT FOR 12 ns; -- Time=2512 ns
		CHECK_wen2('0',2512);
		CHECK_ren2('0',2512);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2612 ns
		CHECK_wen2('0',2612);
		CHECK_ren2('0',2612);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2712 ns
		CHECK_wen2('0',2712);
		CHECK_ren2('0',2712);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2812 ns
		CHECK_wen2('0',2812);
		CHECK_ren2('0',2812);
		-- --------------------
		WAIT FOR 100 ns; -- Time=2912 ns
		CHECK_wen2('0',2912);
		CHECK_ren2('0',2912);
		-- --------------------
		WAIT FOR 100 ns; -- Time=3012 ns
		CHECK_wen2('0',3012);
		CHECK_ren2('0',3012);
		-- --------------------
		WAIT FOR 100 ns; -- Time=3112 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION ren_wen_cfg OF ren_wen_tbw IS
	FOR testbench_arch
	END FOR;
END ren_wen_cfg;