version 3
ren_wen.vhd
ren_wen
VHDL
VHDL
ren_wen_tbw.xwv
Clocked
-
-
610000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
50000000
50000000
6000000
6000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
reset
clk
decim_ratio
clk
decim_en
clk
decim_flag
clk
enable_w
clk
enable_r
clk
wen2
clk
ren2
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
SIGNAL_ORDER_END
-X-X-X-
NOTE: This file was converted from the Granite version