-- E:\XILINX\CHANNELCTRL\CHNCTRL
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Sun Jun 11 20:36:43 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY ren_wen_tbw IS
END ren_wen_tbw;

ARCHITECTURE testbench_arch OF ren_wen_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "e:\xilinx\channelctrl\chnctrl\ren_wen_tbw.ano";
	COMPONENT ren_wen
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			decim_ratio : In  std_logic_vector (1 DOWNTO 0);
			decim_en : In  std_logic;
			decim_flag : In  std_logic;
			enable_r : In  std_logic;
			enable_w : In  std_logic;
			wen2 : Out  std_logic;
			ren2 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL decim_ratio : std_logic_vector (1 DOWNTO 0);
	SIGNAL decim_en : std_logic;
	SIGNAL decim_flag : std_logic;
	SIGNAL enable_r : std_logic;
	SIGNAL enable_w : std_logic;
	SIGNAL wen2 : std_logic;
	SIGNAL ren2 : std_logic;

BEGIN
	UUT : ren_wen
	PORT MAP (
		reset => reset,
		clk => clk,
		decim_ratio => decim_ratio,
		decim_en => decim_en,
		decim_flag => decim_flag,
		enable_r => enable_r,
		enable_w => enable_w,
		wen2 => wen2,
		ren2 => ren2
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_wen2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",wen2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ren2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ren2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		clk <= transport '1';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		ANNOTATE_wen2(TX_TIME);
		ANNOTATE_ren2(TX_TIME);
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		clk <= transport '0';
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		decim_ratio <= transport std_logic_vector'("01"); --1
		decim_en <= transport '1';
		decim_flag <= transport '0';
		enable_w <= transport '1';
		enable_r <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		decim_en <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		enable_w <= transport '0';
		-- --------------------
		WAIT FOR 600 ns; -- Time=1200 ns
		decim_flag <= transport '1';
		-- --------------------
		WAIT FOR 400 ns; -- Time=1600 ns
		decim_flag <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1700 ns
		enable_r <= transport '0';
		-- --------------------
		WAIT FOR 800 ns; -- Time=2500 ns
		decim_flag <= transport '1';
		-- --------------------
		WAIT FOR 612 ns; -- Time=3112 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION ren_wen_cfg OF ren_wen_tbw IS
	FOR testbench_arch
	END FOR;
END ren_wen_cfg;