-- VHDL Instantiation Created from source file ren_wen.vhd -- 14:17:31 02/26/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT ren_wen
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		decim_ratio : IN std_logic_vector(1 downto 0);
		decim_en : IN std_logic;
		decim_flag : IN std_logic;
		enable_r : IN std_logic;
		enable_w : IN std_logic;          
		wen2 : OUT std_logic;
		ren2 : OUT std_logic
		);
	END COMPONENT;

	Inst_ren_wen: ren_wen PORT MAP(
		reset => ,
		clk => ,
		decim_ratio => ,
		decim_en => ,
		decim_flag => ,
		enable_r => ,
		enable_w => ,
		wen2 => ,
		ren2 => 
	);