Release 6.1.03i - xst G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: ren_wen.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : ren_wen.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : ren_wen
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : ren_wen
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : ren_wen.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work.
Architecture behavioral of Entity decim is up to date.
Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work.
Architecture behavioral of Entity ren_wen is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ren_wen> (Architecture <behavioral>).
Entity <ren_wen> analyzed. Unit <ren_wen> generated.

Analyzing Entity <decim> (Architecture <behavioral>).
Entity <decim> analyzed. Unit <decim> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <decim>.
    Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd.
    Found 3-bit comparator less for signal <$n0006> created at line 61.
    Found 3-bit adder for signal <$n0015> created at line 62.
    Found 3-bit register for signal <cnt>.
    Summary:
	inferred   1 Adder/Subtracter(s).
	inferred   1 Comparator(s).
Unit <decim> synthesized.


Synthesizing Unit <ren_wen>.
    Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd.
Unit <ren_wen> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  3-bit register                   : 1
# Adders/Subtractors               : 1
  3-bit adder                      : 1
# Comparators                      : 1
  3-bit comparator less            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ren_wen> ...

Optimizing unit <decim> ...
  implementation constraint: INIT=s	 : cnt_0
  implementation constraint: INIT=s	 : cnt_1
  implementation constraint: INIT=s	 : cnt_2

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : ren_wen.ngr
Top Level Output File Name         : ren_wen
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 10

Macro Statistics :
# Registers                        : 3
#      1-bit register              : 3
# Comparators                      : 1
#      3-bit comparator less       : 1
# Xors                             : 2
#      1-bit xor2                  : 2

Cell Usage :
# BELS                             : 32
#      AND2                        : 10
#      AND3                        : 1
#      INV                         : 16
#      OR2                         : 3
#      XOR2                        : 2
# FlipFlops/Latches                : 3
#      FDCE                        : 3
# IO Buffers                       : 10
#      IBUF                        : 8
#      OBUF                        : 2
=========================================================================
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