-- VHDL Instantiation Created from source file fsm1.vhd -- 11:05:34 06/12/2006
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT fsm1
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		acqen : IN std_logic;
		trigmode : IN std_logic;
		trigger : IN std_logic;
		decim_ratio : IN std_logic_vector(1 downto 0);
		ptrig_data : IN std_logic_vector(1 downto 0);
		rstdataready : IN std_logic;          
		rst1 : OUT std_logic;
		wen1 : OUT std_logic;
		ren1 : OUT std_logic;
		rst2 : OUT std_logic;
		wen2 : OUT std_logic;
		ren2 : OUT std_logic;
		rst3 : OUT std_logic;
		wen3 : OUT std_logic;
		trigger_en : OUT std_logic;
		decim_flag : OUT std_logic;
		dataready : OUT std_logic
		);
	END COMPONENT;

	Inst_fsm1: fsm1 PORT MAP(
		reset => ,
		clk => ,
		acqen => ,
		trigmode => ,
		trigger => ,
		decim_ratio => ,
		ptrig_data => ,
		rstdataready => ,
		rst1 => ,
		wen1 => ,
		ren1 => ,
		rst2 => ,
		wen2 => ,
		ren2 => ,
		rst3 => ,
		wen3 => ,
		trigger_en => ,
		decim_flag => ,
		dataready => 
	);