Release 6.1.03i - xst G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.10 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.10 s | Elapsed : 0.00 / 0.00 s --> Reading design: fsm1.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : fsm1.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : fsm1 Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : fsm1 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : fsm1.lso verilog2001 : YES Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110 111" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fsm1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 8 | | Transitions | 25 | | Inputs | 9 | | Outputs | 12 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0039> created at line 502. Found 12-bit comparator less for signal <$n0040> created at line 536. Found 12-bit comparator less for signal <$n0041> created at line 565. Found 12-bit comparator less for signal <$n0042> created at line 590. Found 5-bit comparator greatequal for signal <$n0047> created at line 502. Found 12-bit comparator greatequal for signal <$n0048> created at line 536. Found 12-bit adder for signal <$n0049> created at line 591. Found 5-bit up counter for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 5 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 6 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 7 3-bit register : 1 1-bit register : 5 12-bit register : 1 # Counters : 2 5-bit up counter : 1 12-bit up counter : 1 # Adders/Subtractors : 2 3-bit adder : 1 12-bit adder : 1 # Comparators : 7 3-bit comparator less : 1 5-bit comparator less : 1 12-bit comparator less : 3 5-bit comparator greatequal : 1 12-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_delay_1 implementation constraint: INIT=s : cnt_delay_2 implementation constraint: INIT=s : cnt_delay_3 implementation constraint: INIT=s : cnt_record_9 implementation constraint: INIT=s : cnt_delay_0 implementation constraint: INIT=s : cnt_delay_4 implementation constraint: INIT=s : cnt_transfer_9 implementation constraint: INIT=s : cnt_record_6 implementation constraint: INIT=s : cnt_record_8 implementation constraint: INIT=s : cnt_record_7 implementation constraint: INIT=s : cnt_transfer_11 implementation constraint: INIT=s : cnt_transfer_10 implementation constraint: INIT=r : cnt_transfer_0 implementation constraint: INIT=r : cnt_transfer_1 implementation constraint: INIT=s : cnt_transfer_2 implementation constraint: INIT=r : cnt_transfer_3 implementation constraint: INIT=s : cnt_transfer_4 implementation constraint: INIT=s : cnt_transfer_5 implementation constraint: INIT=s : cnt_transfer_6 implementation constraint: INIT=s : cnt_transfer_7 implementation constraint: INIT=s : cnt_transfer_8 implementation constraint: INIT=s : cnt_record_11 implementation constraint: INIT=s : cnt_record_10 implementation constraint: INIT=r : cnt_record_0 implementation constraint: INIT=r : cnt_record_1 implementation constraint: INIT=s : cnt_record_2 implementation constraint: INIT=r : cnt_record_3 implementation constraint: INIT=s : cnt_record_4 implementation constraint: INIT=s : cnt_record_5 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : fsm1.ngr Top Level Output File Name : fsm1 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : xc9500xl Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 21 Macro Statistics : # Registers : 17 # 1-bit register : 17 # Comparators : 7 # 12-bit comparator greatequal: 1 # 12-bit comparator less : 3 # 3-bit comparator less : 1 # 5-bit comparator greatequal : 1 # 5-bit comparator less : 1 # Xors : 44 # 1-bit xor2 : 44 Cell Usage : # BELS : 283 # AND2 : 90 # AND3 : 15 # AND4 : 2 # AND5 : 3 # AND8 : 1 # INV : 116 # OR2 : 23 # OR3 : 1 # VCC : 1 # XOR2 : 31 # FlipFlops/Latches : 40 # FDCE : 33 # FDP : 1 # FDPE : 3 # FTC : 3 # IO Buffers : 21 # IBUF : 10 # OBUF : 11 ========================================================================= CPU : 0.82 / 0.98 s | Elapsed : 0.00 / 1.00 s --> Total memory usage is 47776 kilobytes