info x 533 510 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VHDL
col x 516 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
radix x 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
entity name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 fifo3
term mark 416 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
vlib save 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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Thu Feb 26 12:32:31 2004
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type info 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 std_logicBITDOWNTO
opt vhdl87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
NumClocks x 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
clock_1 name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clk
Zoom_level x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.06250000000000