-- VHDL Instantiation Created from source file fifo3.vhd -- 05:59:42 12/07/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT fifo3
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		acqen : IN std_logic;
		tmode : IN std_logic;
		fifo3_en : IN std_logic;
		rstdataready : IN std_logic;          
		dataready : OUT std_logic;
		rst3 : OUT std_logic;
		wen3 : OUT std_logic
		);
	END COMPONENT;

	Inst_fifo3: fifo3 PORT MAP(
		reset => ,
		clk => ,
		acqen => ,
		tmode => ,
		fifo3_en => ,
		rstdataready => ,
		dataready => ,
		rst3 => ,
		wen3 => 
	);