-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Jun 09 16:28:41 2006

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY fifo2ctrl_tbw IS
END fifo2ctrl_tbw;

ARCHITECTURE testbench_arch OF fifo2ctrl_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\channelctrl\chnctrl\fifo2ctrl_tbw.ano";
	COMPONENT fifo2
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			acqen : In  std_logic;
			trigmode : In  std_logic;
			trigger : In  std_logic;
			ren1 : In  std_logic;
			decim_ratio : In  std_logic_vector (1 DOWNTO 0);
			n1param : In  std_logic_vector (1 DOWNTO 0);
			rstdataready : In  std_logic;
			dataready : In  std_logic;
			rst2 : Out  std_logic;
			wen2 : Out  std_logic;
			ren2 : Out  std_logic;
			trigger_en : Out  std_logic;
			decim_flag : Out  std_logic;
			fifo3_en : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL acqen : std_logic;
	SIGNAL trigmode : std_logic;
	SIGNAL trigger : std_logic;
	SIGNAL ren1 : std_logic;
	SIGNAL decim_ratio : std_logic_vector (1 DOWNTO 0);
	SIGNAL n1param : std_logic_vector (1 DOWNTO 0);
	SIGNAL rstdataready : std_logic;
	SIGNAL dataready : std_logic;
	SIGNAL rst2 : std_logic;
	SIGNAL wen2 : std_logic;
	SIGNAL ren2 : std_logic;
	SIGNAL trigger_en : std_logic;
	SIGNAL decim_flag : std_logic;
	SIGNAL fifo3_en : std_logic;

BEGIN
	UUT : fifo2
	PORT MAP (
		reset => reset,
		clk => clk,
		acqen => acqen,
		trigmode => trigmode,
		trigger => trigger,
		ren1 => ren1,
		decim_ratio => decim_ratio,
		n1param => n1param,
		rstdataready => rstdataready,
		dataready => dataready,
		rst2 => rst2,
		wen2 => wen2,
		ren2 => ren2,
		trigger_en => trigger_en,
		decim_flag => decim_flag,
		fifo3_en => fifo3_en
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_rst2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rst2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_wen2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",wen2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ren2(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ren2,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren2);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_trigger_en(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",trigger_en,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, trigger_en);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_decim_flag(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",decim_flag,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, decim_flag);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_fifo3_en(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",fifo3_en,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, fifo3_en);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		clk <= transport '1';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		ANNOTATE_rst2(TX_TIME);
		ANNOTATE_wen2(TX_TIME);
		ANNOTATE_ren2(TX_TIME);
		ANNOTATE_trigger_en(TX_TIME);
		ANNOTATE_decim_flag(TX_TIME);
		ANNOTATE_fifo3_en(TX_TIME);
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		clk <= transport '0';
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		acqen <= transport '1';
		trigger <= transport '0';
		ren1 <= transport '1';
		decim_ratio <= transport std_logic_vector'("01"); --1
		n1param <= transport std_logic_vector'("00"); --0
		trigmode <= transport '0';
		rstdataready <= transport '1';
		dataready <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 500 ns; -- Time=700 ns
		acqen <= transport '0';
		-- --------------------
		WAIT FOR 700 ns; -- Time=1400 ns
		ren1 <= transport '0';
		-- --------------------
		WAIT FOR 3100 ns; -- Time=4500 ns
		trigger <= transport '1';
		-- --------------------
		WAIT FOR 4200 ns; -- Time=8700 ns
		trigger <= transport '0';
		-- --------------------
		WAIT FOR 3300 ns; -- Time=12000 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=12100 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=12300 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=12400 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=12500 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=12600 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 600 ns; -- Time=13200 ns
		trigger <= transport '1';
		-- --------------------
		WAIT FOR 6300 ns; -- Time=19500 ns
		rstdataready <= transport '0';
		-- --------------------
		WAIT FOR 400 ns; -- Time=19900 ns
		rstdataready <= transport '1';
		-- --------------------
		WAIT FOR 8500 ns; -- Time=28400 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION fifo2_cfg OF fifo2ctrl_tbw IS
	FOR testbench_arch
	END FOR;
END fifo2_cfg;