-- Xilinx Vhdl netlist produced by netgen application (version G.26) -- Command : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim fifo2.nga fifo2_timesim.vhd -- Input file : fifo2.nga -- Output file : fifo2_timesim.vhd -- Design name : fifo2.nga -- # of Entities : 1 -- Xilinx : C:/Xilinx -- Device : XC9572XL-5-VQ44 (Speed File: Version 3.0) -- This vhdl netlist is a simulation model and uses simulation -- primitives which may not represent the true implementation of the -- device, however the netlist is functionally correct and should not -- be modified. This file cannot be synthesized and should only be used -- with supported simulation tools. library IEEE; use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM; use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity fifo2 is port ( trig_mode : in STD_LOGIC := 'X'; acqen : in STD_LOGIC := 'X'; acqclk : in STD_LOGIC := 'X'; reset : in STD_LOGIC := 'X'; ren1 : in STD_LOGIC := 'X'; trigger : in STD_LOGIC := 'X'; decim_flag : out STD_LOGIC; counten : out STD_LOGIC; ren2 : out STD_LOGIC; rst2 : out STD_LOGIC; trigger_en : out STD_LOGIC; wen2 : out STD_LOGIC; n1param : in STD_LOGIC_VECTOR ( 1 downto 0 ); decim_ratio : in STD_LOGIC_VECTOR ( 1 downto 0 ); fsmst : out STD_LOGIC_VECTOR ( 2 downto 0 ) ); end fifo2; architecture Structure of fifo2 is signal trig_mode_IBUF : STD_LOGIC; signal acqen_IBUF : STD_LOGIC; signal FCLKIO_0 : STD_LOGIC; signal reset_IBUF : STD_LOGIC; signal FSR_IO_1 : STD_LOGIC; signal n1param_1_IBUF : STD_LOGIC; signal n1param_0_IBUF : STD_LOGIC; signal ren1_IBUF : STD_LOGIC; signal trigger_IBUF : STD_LOGIC; signal decim_ratio_0_IBUF : STD_LOGIC; signal decim_ratio_1_IBUF : STD_LOGIC; signal decim_flag_OBUF_Q : STD_LOGIC; signal fsmst_0 : STD_LOGIC; signal fsmst_1 : STD_LOGIC; signal fsmst_2 : STD_LOGIC; signal counten_OBUF : STD_LOGIC; signal ren2_OBUF : STD_LOGIC; signal rst2_OBUF : STD_LOGIC; signal trigger_en_OBUF_Q : STD_LOGIC; signal wen2_OBUF : STD_LOGIC; signal cnt_val_4_Q : STD_LOGIC; signal cnt_val_4_EXP_tsimrenamed_net_Q : STD_LOGIC; signal cnt_val_4_EXP : STD_LOGIC; signal cnt_val_4_D : STD_LOGIC; signal PRLD : STD_LOGIC; signal cnt_val_4_RSTF : STD_LOGIC; signal Vcc : STD_LOGIC; signal cnt_val_4_D1 : STD_LOGIC; signal cnt_val_4_D2 : STD_LOGIC; signal EXP9_EXP : STD_LOGIC; signal cnt_val_4_D2_PT_0 : STD_LOGIC; signal state_FFT3 : STD_LOGIC; signal cnt_val_4_D2_PT_1 : STD_LOGIC; signal state_FFT2 : STD_LOGIC; signal state_FFT1 : STD_LOGIC; signal cnt_val_4_EXP_PT_0 : STD_LOGIC; signal cnt_val_4_EXP_PT_1 : STD_LOGIC; signal cnt_val_4_EXP_PT_2 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_D : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_D1 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_D2 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1 : STD_LOGIC; signal cnt_val_0_Q : STD_LOGIC; signal cnt_val_0_EXP_tsimrenamed_net_Q : STD_LOGIC; signal cnt_val_0_EXP : STD_LOGIC; signal cnt_val_0_D : STD_LOGIC; signal cnt_val_0_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_0_RSTF : STD_LOGIC; signal cnt_val_0_D1 : STD_LOGIC; signal cnt_val_0_D2 : STD_LOGIC; signal EXP8_EXP : STD_LOGIC; signal cnt_val_0_D2_PT_0 : STD_LOGIC; signal cnt_val_0_D2_PT_1 : STD_LOGIC; signal cnt_val_0_EXP_PT_0 : STD_LOGIC; signal cnt_val_0_EXP_PT_1 : STD_LOGIC; signal cnt_val_0_EXP_PT_2 : STD_LOGIC; signal cnt_val_1_Q : STD_LOGIC; signal cnt_val_1_EXP_tsimrenamed_net_Q : STD_LOGIC; signal cnt_val_1_EXP : STD_LOGIC; signal cnt_val_1_D : STD_LOGIC; signal cnt_val_1_RSTF : STD_LOGIC; signal cnt_val_1_D1 : STD_LOGIC; signal cnt_val_1_D2 : STD_LOGIC; signal EXP10_EXP : STD_LOGIC; signal cnt_val_1_D2_PT_0 : STD_LOGIC; signal cnt_val_1_D2_PT_1 : STD_LOGIC; signal cnt_val_1_EXP_PT_0 : STD_LOGIC; signal cnt_val_1_EXP_PT_1 : STD_LOGIC; signal cnt_val_1_EXP_PT_2 : STD_LOGIC; signal cnt_val_2_Q : STD_LOGIC; signal cnt_val_2_D : STD_LOGIC; signal cnt_val_2_RSTF : STD_LOGIC; signal cnt_val_2_D1 : STD_LOGIC; signal cnt_val_2_D2 : STD_LOGIC; signal cnt_val_3_EXP : STD_LOGIC; signal cnt_val_2_D2_PT_0 : STD_LOGIC; signal EXP12_EXP : STD_LOGIC; signal cnt_val_2_D2_PT_1 : STD_LOGIC; signal cnt_val_2_D2_PT_2 : STD_LOGIC; signal cnt_val_2_D2_PT_3 : STD_LOGIC; signal cnt_val_2_D2_PT_4 : STD_LOGIC; signal cnt_val_2_D2_PT_5 : STD_LOGIC; signal cnt_val_3_Q : STD_LOGIC; signal cnt_val_3_EXP_tsimrenamed_net_Q : STD_LOGIC; signal cnt_val_3_D : STD_LOGIC; signal cnt_val_3_RSTF : STD_LOGIC; signal cnt_val_3_D1 : STD_LOGIC; signal cnt_val_3_D2 : STD_LOGIC; signal EXP11_EXP : STD_LOGIC; signal cnt_val_3_D2_PT_0 : STD_LOGIC; signal cnt_val_3_D2_PT_1 : STD_LOGIC; signal cnt_val_3_D2_PT_2 : STD_LOGIC; signal cnt_val_3_EXP_PT_0 : STD_LOGIC; signal cnt_val_3_EXP_PT_1 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_D : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_D1 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_D2 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1 : STD_LOGIC; signal cnt_val_10_Q : STD_LOGIC; signal cnt_val_10_D : STD_LOGIC; signal cnt_val_10_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_10_RSTF : STD_LOGIC; signal cnt_val_10_D1 : STD_LOGIC; signal cnt_val_10_D2 : STD_LOGIC; signal cnt_val_10_D2_PT_0 : STD_LOGIC; signal cnt_val_10_D2_PT_1 : STD_LOGIC; signal cnt_val_5_Q : STD_LOGIC; signal cnt_val_5_D : STD_LOGIC; signal cnt_val_5_RSTF : STD_LOGIC; signal cnt_val_5_D1 : STD_LOGIC; signal cnt_val_5_D2 : STD_LOGIC; signal EXP7_EXP : STD_LOGIC; signal cnt_val_5_D2_PT_0 : STD_LOGIC; signal cnt_val_5_D2_PT_1 : STD_LOGIC; signal cnt_val_5_D2_PT_2 : STD_LOGIC; signal cnt_val_5_D2_PT_3 : STD_LOGIC; signal cnt_val_5_D2_PT_4 : STD_LOGIC; signal cnt_val_6_Q : STD_LOGIC; signal cnt_val_6_D : STD_LOGIC; signal cnt_val_6_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_6_RSTF : STD_LOGIC; signal cnt_val_6_D1 : STD_LOGIC; signal cnt_val_6_D2 : STD_LOGIC; signal cnt_val_6_D2_PT_0 : STD_LOGIC; signal cnt_val_6_D2_PT_1 : STD_LOGIC; signal cnt_val_7_Q : STD_LOGIC; signal cnt_val_7_D : STD_LOGIC; signal cnt_val_7_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_7_RSTF : STD_LOGIC; signal cnt_val_7_D1 : STD_LOGIC; signal cnt_val_7_D2 : STD_LOGIC; signal cnt_val_7_D2_PT_0 : STD_LOGIC; signal cnt_val_7_D2_PT_1 : STD_LOGIC; signal cnt_val_8_Q : STD_LOGIC; signal cnt_val_8_D : STD_LOGIC; signal cnt_val_8_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_8_RSTF : STD_LOGIC; signal cnt_val_8_D1 : STD_LOGIC; signal cnt_val_8_D2 : STD_LOGIC; signal cnt_val_8_D2_PT_0 : STD_LOGIC; signal cnt_val_8_D2_PT_1 : STD_LOGIC; signal cnt_val_9_Q : STD_LOGIC; signal cnt_val_9_D : STD_LOGIC; signal cnt_val_9_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_9_RSTF : STD_LOGIC; signal cnt_val_9_D1 : STD_LOGIC; signal cnt_val_9_D2 : STD_LOGIC; signal cnt_val_9_D2_PT_0 : STD_LOGIC; signal cnt_val_9_D2_PT_1 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_D : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_D1 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_D2 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_D2_PT_0 : STD_LOGIC; signal Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1 : STD_LOGIC; signal cnt_val_11_Q : STD_LOGIC; signal cnt_val_11_D : STD_LOGIC; signal cnt_val_11_tsimcreated_xor_Q : STD_LOGIC; signal cnt_val_11_RSTF : STD_LOGIC; signal cnt_val_11_D1 : STD_LOGIC; signal cnt_val_11_D2 : STD_LOGIC; signal cnt_val_11_D2_PT_0 : STD_LOGIC; signal cnt_val_11_D2_PT_1 : STD_LOGIC; signal cnt_ovf1_Q : STD_LOGIC; signal cnt_ovf1 : STD_LOGIC; signal cnt_ovf1_D : STD_LOGIC; signal cnt_ovf1_SETF : STD_LOGIC; signal cnt_ovf1_D1 : STD_LOGIC; signal cnt_ovf1_D2 : STD_LOGIC; signal rst2_OBUF_EXP : STD_LOGIC; signal cnt_ovf1_D2_PT_0 : STD_LOGIC; signal EXP14_EXP : STD_LOGIC; signal cnt_ovf1_D2_PT_1 : STD_LOGIC; signal cnt_ovf1_D2_PT_2 : STD_LOGIC; signal cnt_ovf1_D2_PT_3 : STD_LOGIC; signal cnt_ovf1_D2_PT_4 : STD_LOGIC; signal cnt_ovf1_D2_PT_5 : STD_LOGIC; signal state_FFT2_Q : STD_LOGIC; signal state_FFT2_D : STD_LOGIC; signal state_FFT2_tsimcreated_xor_Q : STD_LOGIC; signal state_FFT2_tsimcreated_prld_Q : STD_LOGIC; signal Gnd : STD_LOGIC; signal state_FFT2_D1 : STD_LOGIC; signal state_FFT2_D2 : STD_LOGIC; signal state_FFT2_D2_PT_0 : STD_LOGIC; signal state_FFT2_D2_PT_1 : STD_LOGIC; signal cnt_ovf2 : STD_LOGIC; signal state_FFT2_D2_PT_2 : STD_LOGIC; signal state_FFT2_D2_PT_3 : STD_LOGIC; signal state_FFT2_D2_PT_4 : STD_LOGIC; signal state_FFT1_Q : STD_LOGIC; signal state_FFT1_D : STD_LOGIC; signal state_FFT1_tsimcreated_xor_Q : STD_LOGIC; signal state_FFT1_tsimcreated_prld_Q : STD_LOGIC; signal state_FFT1_D1 : STD_LOGIC; signal state_FFT1_D2 : STD_LOGIC; signal state_FFT1_D2_PT_0 : STD_LOGIC; signal state_FFT1_D2_PT_1 : STD_LOGIC; signal state_FFT1_D2_PT_2 : STD_LOGIC; signal state_FFT1_D2_PT_3 : STD_LOGIC; signal state_FFT3_Q : STD_LOGIC; signal state_FFT3_D : STD_LOGIC; signal state_FFT3_tsimcreated_xor_Q : STD_LOGIC; signal state_FFT3_tsimcreated_prld_Q : STD_LOGIC; signal state_FFT3_D1 : STD_LOGIC; signal state_FFT3_D2 : STD_LOGIC; signal cnt_ovf2_Q : STD_LOGIC; signal cnt_ovf2_D : STD_LOGIC; signal cnt_ovf2_D1 : STD_LOGIC; signal cnt_ovf2_D2 : STD_LOGIC; signal EXP15_EXP : STD_LOGIC; signal cnt_ovf2_D2_PT_0 : STD_LOGIC; signal cnt_ovf2_D2_PT_1 : STD_LOGIC; signal cnt_ovf2_D2_PT_2 : STD_LOGIC; signal cnt_ovf2_D2_PT_3 : STD_LOGIC; signal cnt_ovf2_D2_PT_4 : STD_LOGIC; signal cnt_ovf2_D2_PT_5 : STD_LOGIC; signal decim_flag_OBUF_Q_0 : STD_LOGIC; signal decim_flag_OBUF_D : STD_LOGIC; signal decim_flag_OBUF_D1 : STD_LOGIC; signal decim_flag_OBUF_D2 : STD_LOGIC; signal decim_flag_OBUF_D2_PT_0 : STD_LOGIC; signal decim_flag_OBUF_D2_PT_1 : STD_LOGIC; signal fsmst_0_Q : STD_LOGIC; signal fsmst_0_RSTF : STD_LOGIC; signal fsmst_0_SETF : STD_LOGIC; signal fsmst_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; signal fsmst_0_tsimcreated_prld_Q : STD_LOGIC; signal fsmst_0_D : STD_LOGIC; signal fsmst_0_CLKF : STD_LOGIC; signal fsmst_0_D1 : STD_LOGIC; signal fsmst_0_D2 : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_UIM : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_UIM : STD_LOGIC; signal fsmst_1_Q : STD_LOGIC; signal fsmst_1_RSTF : STD_LOGIC; signal fsmst_1_SETF : STD_LOGIC; signal fsmst_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; signal fsmst_1_tsimcreated_prld_Q : STD_LOGIC; signal fsmst_1_D : STD_LOGIC; signal fsmst_1_CLKF : STD_LOGIC; signal fsmst_1_D1 : STD_LOGIC; signal fsmst_1_D2 : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_UIM : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_UIM : STD_LOGIC; signal fsmst_2_Q : STD_LOGIC; signal fsmst_2_RSTF : STD_LOGIC; signal fsmst_2_SETF : STD_LOGIC; signal fsmst_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; signal fsmst_2_tsimcreated_prld_Q : STD_LOGIC; signal fsmst_2_D : STD_LOGIC; signal fsmst_2_CLKF : STD_LOGIC; signal fsmst_2_D1 : STD_LOGIC; signal fsmst_2_D2 : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_UIM : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_UIM : STD_LOGIC; signal counten_OBUF_Q : STD_LOGIC; signal counten_OBUF_D : STD_LOGIC; signal counten_OBUF_D1 : STD_LOGIC; signal counten_OBUF_D2 : STD_LOGIC; signal counten_OBUF_D2_PT_0 : STD_LOGIC; signal counten_OBUF_D2_PT_1 : STD_LOGIC; signal ren2_OBUF_Q : STD_LOGIC; signal ren2_OBUF_D : STD_LOGIC; signal ren2_OBUF_D1 : STD_LOGIC; signal ren2_OBUF_D2 : STD_LOGIC; signal ren2_OBUF_D2_PT_0 : STD_LOGIC; signal ren2_OBUF_D2_PT_1 : STD_LOGIC; signal ren2_OBUF_D2_PT_2 : STD_LOGIC; signal ren2_OBUF_D2_PT_3 : STD_LOGIC; signal rst2_OBUF_Q : STD_LOGIC; signal rst2_OBUF_EXP_tsimrenamed_net_Q : STD_LOGIC; signal rst2_OBUF_D : STD_LOGIC; signal rst2_OBUF_D1 : STD_LOGIC; signal rst2_OBUF_D2 : STD_LOGIC; signal EXP6_EXP : STD_LOGIC; signal rst2_OBUF_EXP_PT_0 : STD_LOGIC; signal rst2_OBUF_EXP_PT_1 : STD_LOGIC; signal rst2_OBUF_EXP_PT_2 : STD_LOGIC; signal rst2_OBUF_EXP_PT_3 : STD_LOGIC; signal rst2_OBUF_EXP_PT_4 : STD_LOGIC; signal trigger_en_OBUF_Q_1 : STD_LOGIC; signal trigger_en_OBUF_D : STD_LOGIC; signal trigger_en_OBUF_D1 : STD_LOGIC; signal trigger_en_OBUF_D2 : STD_LOGIC; signal wen2_OBUF_Q : STD_LOGIC; signal wen2_OBUF_D : STD_LOGIC; signal wen2_OBUF_D1 : STD_LOGIC; signal wen2_OBUF_D2 : STD_LOGIC; signal wen2_OBUF_D2_PT_0 : STD_LOGIC; signal wen2_OBUF_D2_PT_1 : STD_LOGIC; signal wen2_OBUF_D2_PT_2 : STD_LOGIC; signal wen2_OBUF_D2_PT_3 : STD_LOGIC; signal wen2_OBUF_D2_PT_4 : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_Q : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_D : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_D1 : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_D2 : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_D2_PT_0 : STD_LOGIC; signal fsmst_0_fsmst_0_SETF_D2_PT_1 : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_Q : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D1 : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D2 : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D2_PT_0 : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D2_PT_1 : STD_LOGIC; signal fsmst_0_fsmst_0_RSTF_INT_D2_PT_2 : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_Q : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_D : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_D1 : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_D2 : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_D2_PT_0 : STD_LOGIC; signal fsmst_1_fsmst_1_SETF_D2_PT_1 : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_Q : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_D : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_D1 : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_D2 : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_D2_PT_0 : STD_LOGIC; signal fsmst_1_fsmst_1_RSTF_D2_PT_1 : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_Q : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_D : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_D1 : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_D2 : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_D2_PT_0 : STD_LOGIC; signal fsmst_2_fsmst_2_SETF_D2_PT_1 : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_Q : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_D : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_D1 : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_D2 : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_D2_PT_0 : STD_LOGIC; signal fsmst_2_fsmst_2_RSTF_D2_PT_1 : STD_LOGIC; signal EXP6_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP7_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP7_EXP_PT_0 : STD_LOGIC; signal EXP7_EXP_PT_1 : STD_LOGIC; signal EXP8_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP8_EXP_PT_0 : STD_LOGIC; signal EXP8_EXP_PT_1 : STD_LOGIC; signal EXP8_EXP_PT_2 : STD_LOGIC; signal EXP8_EXP_PT_3 : STD_LOGIC; signal EXP8_EXP_PT_4 : STD_LOGIC; signal EXP9_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP9_EXP_PT_0 : STD_LOGIC; signal EXP9_EXP_PT_1 : STD_LOGIC; signal EXP9_EXP_PT_2 : STD_LOGIC; signal EXP9_EXP_PT_3 : STD_LOGIC; signal EXP9_EXP_PT_4 : STD_LOGIC; signal EXP9_EXP_PT_5 : STD_LOGIC; signal EXP10_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP10_EXP_PT_0 : STD_LOGIC; signal EXP10_EXP_PT_1 : STD_LOGIC; signal EXP10_EXP_PT_2 : STD_LOGIC; signal EXP10_EXP_PT_3 : STD_LOGIC; signal EXP10_EXP_PT_4 : STD_LOGIC; signal EXP10_EXP_PT_5 : STD_LOGIC; signal EXP11_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP11_EXP_PT_0 : STD_LOGIC; signal EXP11_EXP_PT_1 : STD_LOGIC; signal EXP11_EXP_PT_2 : STD_LOGIC; signal EXP11_EXP_PT_3 : STD_LOGIC; signal EXP11_EXP_PT_4 : STD_LOGIC; signal EXP11_EXP_PT_5 : STD_LOGIC; signal EXP12_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP12_EXP_PT_0 : STD_LOGIC; signal EXP12_EXP_PT_1 : STD_LOGIC; signal EXP12_EXP_PT_2 : STD_LOGIC; signal EXP12_EXP_PT_3 : STD_LOGIC; signal EXP12_EXP_PT_4 : STD_LOGIC; signal EXP13_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP13_EXP : STD_LOGIC; signal EXP13_EXP_PT_0 : STD_LOGIC; signal EXP13_EXP_PT_1 : STD_LOGIC; signal EXP13_EXP_PT_2 : STD_LOGIC; signal EXP13_EXP_PT_3 : STD_LOGIC; signal EXP13_EXP_PT_4 : STD_LOGIC; signal EXP14_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP14_EXP_PT_0 : STD_LOGIC; signal EXP14_EXP_PT_1 : STD_LOGIC; signal EXP14_EXP_PT_2 : STD_LOGIC; signal EXP14_EXP_PT_3 : STD_LOGIC; signal EXP14_EXP_PT_4 : STD_LOGIC; signal EXP14_EXP_PT_5 : STD_LOGIC; signal EXP15_EXP_tsimrenamed_net_Q : STD_LOGIC; signal EXP15_EXP_PT_0 : STD_LOGIC; signal EXP15_EXP_PT_1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_0_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_4_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D_IN0 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_D2_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_0_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_D2_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_0_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_cnt_val_1_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_D2_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_2_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_D2_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_3_EXP_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_10_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_10_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_10_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_10_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_10_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_D2_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_5_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_6_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_6_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_6_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_6_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_6_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_7_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_7_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_7_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_7_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_7_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_8_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_8_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_8_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_8_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_8_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_9_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_9_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_9_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_9_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_9_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_11_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_val_11_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_11_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_val_11_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_val_11_RSTF_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_D2_PT_5_IN10 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_SETF_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_SETF_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf1_SETF_IN2 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT2_D2_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_3_IN2 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_state_FFT1_D2_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_state_FFT3_D2_IN0 : STD_LOGIC; signal NlwInverterSignal_state_FFT3_D2_IN2 : STD_LOGIC; signal NlwInverterSignal_state_FFT3_D2_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN1 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN3 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_cnt_ovf2_D2_PT_5_IN9 : STD_LOGIC; signal NlwInverterSignal_decim_flag_OBUF_D2_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_decim_flag_OBUF_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_RSTF_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_RSTF_IN1 : STD_LOGIC; signal NlwInverterSignal_fsmst_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; signal NlwInverterSignal_counten_OBUF_D_IN0 : STD_LOGIC; signal NlwInverterSignal_counten_OBUF_D2_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_counten_OBUF_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D_IN0 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_ren2_OBUF_D2_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_D_IN0 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN11 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN12 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN9 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN10 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN11 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN12 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN10 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN11 : STD_LOGIC; signal NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN12 : STD_LOGIC; signal NlwInverterSignal_trigger_en_OBUF_D_IN0 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D_IN0 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_wen2_OBUF_D2_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_fsmst_1_fsmst_1_SETF_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_0_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP7_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_1_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_3_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP8_EXP_PT_4_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP9_EXP_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP10_EXP_PT_5_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP11_EXP_PT_5_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_0_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_3_IN13 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP12_EXP_PT_4_IN13 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_0_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_1_IN13 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_2_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_3_IN13 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP13_EXP_PT_4_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_1_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_2_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN1 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_3_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_4_IN12 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP14_EXP_PT_5_IN11 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN3 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_0_IN10 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN0 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN2 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN4 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN5 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN6 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN7 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN8 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN9 : STD_LOGIC; signal NlwInverterSignal_EXP15_EXP_PT_1_IN10 : STD_LOGIC; signal cnt_val : STD_LOGIC_VECTOR ( 11 downto 0 ); signal Inst_ren_wen_Inst_decim_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); begin trig_mode_IBUF_2 : X_BUF port map ( I => trig_mode, O => trig_mode_IBUF ); acqen_IBUF_3 : X_BUF port map ( I => acqen, O => acqen_IBUF ); FCLKIO_0_4 : X_BUF port map ( I => acqclk, O => FCLKIO_0 ); reset_IBUF_5 : X_BUF port map ( I => reset, O => reset_IBUF ); FSR_IO_1_6 : X_INV port map ( I => reset, O => FSR_IO_1 ); n1param_1_IBUF_7 : X_BUF port map ( I => n1param(1), O => n1param_1_IBUF ); n1param_0_IBUF_8 : X_BUF port map ( I => n1param(0), O => n1param_0_IBUF ); ren1_IBUF_9 : X_BUF port map ( I => ren1, O => ren1_IBUF ); trigger_IBUF_10 : X_BUF port map ( I => trigger, O => trigger_IBUF ); decim_ratio_0_IBUF_11 : X_BUF port map ( I => decim_ratio(0), O => decim_ratio_0_IBUF ); decim_ratio_1_IBUF_12 : X_BUF port map ( I => decim_ratio(1), O => decim_ratio_1_IBUF ); decim_flag_13 : X_BUF port map ( I => decim_flag_OBUF_Q, O => decim_flag ); fsmst_0_Q_14 : X_BUF port map ( I => fsmst_0, O => fsmst(0) ); fsmst_1_Q_15 : X_BUF port map ( I => fsmst_1, O => fsmst(1) ); fsmst_2_Q_16 : X_BUF port map ( I => fsmst_2, O => fsmst(2) ); counten_17 : X_BUF port map ( I => counten_OBUF, O => counten ); ren2_18 : X_BUF port map ( I => ren2_OBUF, O => ren2 ); rst2_19 : X_BUF port map ( I => rst2_OBUF, O => rst2 ); trigger_en_20 : X_BUF port map ( I => trigger_en_OBUF_Q, O => trigger_en ); wen2_21 : X_BUF port map ( I => wen2_OBUF, O => wen2 ); cnt_val_4_Q_22 : X_BUF port map ( I => cnt_val_4_Q, O => cnt_val(4) ); cnt_val_4_EXP_23 : X_BUF port map ( I => cnt_val_4_EXP_tsimrenamed_net_Q, O => cnt_val_4_EXP ); cnt_val_4_REG : X_FF port map ( I => cnt_val_4_D, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_4_RSTF, O => cnt_val_4_Q ); Vcc_24 : X_ONE port map ( O => Vcc ); cnt_val_4_D_25 : X_XOR2 port map ( I0 => cnt_val_4_D1, I1 => cnt_val_4_D2, O => cnt_val_4_D ); cnt_val_4_D1_26 : X_ZERO port map ( O => cnt_val_4_D1 ); cnt_val_4_D2_PT_0_27 : X_AND2 port map ( I0 => EXP9_EXP, I1 => EXP9_EXP, O => cnt_val_4_D2_PT_0 ); cnt_val_4_D2_PT_1_28 : X_AND2 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_cnt_val_4_D2_PT_1_IN1, O => cnt_val_4_D2_PT_1 ); cnt_val_4_D2_29 : X_OR2 port map ( I0 => cnt_val_4_D2_PT_0, I1 => cnt_val_4_D2_PT_1, O => cnt_val_4_D2 ); cnt_val_4_RSTF_30 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_4_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_4_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_4_RSTF_IN2, O => cnt_val_4_RSTF ); cnt_val_4_EXP_PT_0_31 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN2, I3 => cnt_val(0), I4 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN4, I5 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN5, I6 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN6, I7 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN7, I8 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN8, I9 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN9, I10 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN10, I11 => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN11, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_4_EXP_PT_0 ); cnt_val_4_EXP_PT_1_32 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN3, I4 => cnt_val(0), I5 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN5, I6 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN7, I8 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN8, I9 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN9, I10 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN10, I11 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN11, I12 => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_4_EXP_PT_1 ); cnt_val_4_EXP_PT_2_33 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN2, I3 => state_FFT1, I4 => cnt_val(0), I5 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN5, I6 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN6, I7 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN7, I8 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN8, I9 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN9, I10 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN10, I11 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN11, I12 => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_4_EXP_PT_2 ); cnt_val_4_EXP_tsimrenamed_net_Q_34 : X_OR3 port map ( I0 => cnt_val_4_EXP_PT_0, I1 => cnt_val_4_EXP_PT_1, I2 => cnt_val_4_EXP_PT_2, O => cnt_val_4_EXP_tsimrenamed_net_Q ); Inst_ren_wen_Inst_decim_cnt_0_Q_35 : X_BUF port map ( I => Inst_ren_wen_Inst_decim_cnt_0_Q, O => Inst_ren_wen_Inst_decim_cnt(0) ); Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q_36 : X_XOR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_0_D, I1 => Inst_ren_wen_Inst_decim_cnt_0_Q, O => Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q ); Inst_ren_wen_Inst_decim_cnt_0_REG : X_FF port map ( I => Inst_ren_wen_Inst_decim_cnt_0_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => FSR_IO_1, O => Inst_ren_wen_Inst_decim_cnt_0_Q ); Inst_ren_wen_Inst_decim_cnt_0_D_37 : X_XOR2 port map ( I0 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D_IN0, I1 => Inst_ren_wen_Inst_decim_cnt_0_D2, O => Inst_ren_wen_Inst_decim_cnt_0_D ); Inst_ren_wen_Inst_decim_cnt_0_D1_38 : X_ZERO port map ( O => Inst_ren_wen_Inst_decim_cnt_0_D1 ); Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_39 : X_AND2 port map ( I0 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0, I1 => state_FFT1, O => Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0 ); Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_40 : X_AND2 port map ( I0 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN0, I1 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1, O => Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1 ); Inst_ren_wen_Inst_decim_cnt_0_D2_41 : X_OR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0, I1 => Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1, O => Inst_ren_wen_Inst_decim_cnt_0_D2 ); cnt_val_0_Q_42 : X_BUF port map ( I => cnt_val_0_Q, O => cnt_val(0) ); cnt_val_0_EXP_43 : X_BUF port map ( I => cnt_val_0_EXP_tsimrenamed_net_Q, O => cnt_val_0_EXP ); cnt_val_0_tsimcreated_xor_Q_44 : X_XOR2 port map ( I0 => cnt_val_0_D, I1 => cnt_val_0_Q, O => cnt_val_0_tsimcreated_xor_Q ); cnt_val_0_REG : X_FF port map ( I => cnt_val_0_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_0_RSTF, O => cnt_val_0_Q ); cnt_val_0_D_45 : X_XOR2 port map ( I0 => cnt_val_0_D1, I1 => cnt_val_0_D2, O => cnt_val_0_D ); cnt_val_0_D1_46 : X_ZERO port map ( O => cnt_val_0_D1 ); cnt_val_0_D2_PT_0_47 : X_AND2 port map ( I0 => EXP8_EXP, I1 => EXP8_EXP, O => cnt_val_0_D2_PT_0 ); cnt_val_0_D2_PT_1_48 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN3, I4 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN4, I5 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN5, I6 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN7, I8 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN8, I9 => NlwInverterSignal_cnt_val_0_D2_PT_1_IN9, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_0_D2_PT_1 ); cnt_val_0_D2_49 : X_OR2 port map ( I0 => cnt_val_0_D2_PT_0, I1 => cnt_val_0_D2_PT_1, O => cnt_val_0_D2 ); cnt_val_0_RSTF_50 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_0_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_0_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_0_RSTF_IN2, O => cnt_val_0_RSTF ); cnt_val_0_EXP_PT_0_51 : X_AND16 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN1, I2 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN2, I3 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN3, I4 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN4, I5 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN5, I6 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN6, I7 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN7, I8 => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_0_EXP_PT_0 ); cnt_val_0_EXP_PT_1_52 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN3, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN7, I8 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN8, I9 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN9, I10 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN10, I11 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN11, I12 => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN12, I13 => cnt_val(3), I14 => cnt_val(2), I15 => Vcc, O => cnt_val_0_EXP_PT_1 ); cnt_val_0_EXP_PT_2_53 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN2, I3 => state_FFT1, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN6, I7 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN7, I8 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN8, I9 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN9, I10 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN10, I11 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN11, I12 => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN12, I13 => cnt_val(3), I14 => cnt_val(2), I15 => Vcc, O => cnt_val_0_EXP_PT_2 ); cnt_val_0_EXP_tsimrenamed_net_Q_54 : X_OR3 port map ( I0 => cnt_val_0_EXP_PT_0, I1 => cnt_val_0_EXP_PT_1, I2 => cnt_val_0_EXP_PT_2, O => cnt_val_0_EXP_tsimrenamed_net_Q ); cnt_val_1_Q_55 : X_BUF port map ( I => cnt_val_1_Q, O => cnt_val(1) ); cnt_val_1_EXP_56 : X_BUF port map ( I => cnt_val_1_EXP_tsimrenamed_net_Q, O => cnt_val_1_EXP ); cnt_val_1_REG : X_FF port map ( I => cnt_val_1_D, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_1_RSTF, O => cnt_val_1_Q ); cnt_val_1_D_57 : X_XOR2 port map ( I0 => cnt_val_1_D1, I1 => cnt_val_1_D2, O => cnt_val_1_D ); cnt_val_1_D1_58 : X_ZERO port map ( O => cnt_val_1_D1 ); cnt_val_1_D2_PT_0_59 : X_AND2 port map ( I0 => EXP10_EXP, I1 => EXP10_EXP, O => cnt_val_1_D2_PT_0 ); cnt_val_1_D2_PT_1_60 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN0, I1 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN1, I2 => cnt_val(1), I3 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN3, I4 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN4, I5 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN5, I6 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN7, I8 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN8, I9 => NlwInverterSignal_cnt_val_1_D2_PT_1_IN9, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_1_D2_PT_1 ); cnt_val_1_D2_61 : X_OR2 port map ( I0 => cnt_val_1_D2_PT_0, I1 => cnt_val_1_D2_PT_1, O => cnt_val_1_D2 ); cnt_val_1_RSTF_62 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_1_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_1_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_1_RSTF_IN2, O => cnt_val_1_RSTF ); cnt_val_1_EXP_PT_0_63 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN3, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN6, I7 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN7, I8 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN8, I9 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN9, I10 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN10, I11 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN11, I12 => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN12, I13 => cnt_val(2), I14 => Vcc, I15 => Vcc, O => cnt_val_1_EXP_PT_0 ); cnt_val_1_EXP_PT_1_64 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN2, I3 => cnt_val(0), I4 => cnt_val(1), I5 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN5, I6 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN7, I8 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN8, I9 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN9, I10 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN10, I11 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN11, I12 => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN12, I13 => cnt_val(2), I14 => Vcc, I15 => Vcc, O => cnt_val_1_EXP_PT_1 ); cnt_val_1_EXP_PT_2_65 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN1, I2 => state_FFT1, I3 => cnt_val(0), I4 => cnt_val(1), I5 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN5, I6 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN6, I7 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN7, I8 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN8, I9 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN9, I10 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN10, I11 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN11, I12 => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN12, I13 => cnt_val(2), I14 => Vcc, I15 => Vcc, O => cnt_val_1_EXP_PT_2 ); cnt_val_1_EXP_tsimrenamed_net_Q_66 : X_OR3 port map ( I0 => cnt_val_1_EXP_PT_0, I1 => cnt_val_1_EXP_PT_1, I2 => cnt_val_1_EXP_PT_2, O => cnt_val_1_EXP_tsimrenamed_net_Q ); cnt_val_2_Q_67 : X_BUF port map ( I => cnt_val_2_Q, O => cnt_val(2) ); cnt_val_2_REG : X_FF port map ( I => cnt_val_2_D, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_2_RSTF, O => cnt_val_2_Q ); cnt_val_2_D_68 : X_XOR2 port map ( I0 => cnt_val_2_D1, I1 => cnt_val_2_D2, O => cnt_val_2_D ); cnt_val_2_D1_69 : X_ZERO port map ( O => cnt_val_2_D1 ); cnt_val_2_D2_PT_0_70 : X_AND2 port map ( I0 => cnt_val_3_EXP, I1 => cnt_val_3_EXP, O => cnt_val_2_D2_PT_0 ); cnt_val_2_D2_PT_1_71 : X_AND2 port map ( I0 => EXP12_EXP, I1 => EXP12_EXP, O => cnt_val_2_D2_PT_1 ); cnt_val_2_D2_PT_2_72 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN0, I1 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN1, I2 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN2, I3 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN3, I4 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN4, I5 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN5, I6 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN6, I7 => NlwInverterSignal_cnt_val_2_D2_PT_2_IN7, I8 => cnt_val(2), I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_2_D2_PT_2 ); cnt_val_2_D2_PT_3_73 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN0, I1 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN1, I2 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN2, I3 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN3, I4 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN4, I5 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN5, I6 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN6, I7 => NlwInverterSignal_cnt_val_2_D2_PT_3_IN7, I8 => cnt_val(2), I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_2_D2_PT_3 ); cnt_val_2_D2_PT_4_74 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN0, I1 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN1, I2 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN2, I3 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN3, I4 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN4, I5 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN5, I6 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN6, I7 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN7, I8 => NlwInverterSignal_cnt_val_2_D2_PT_4_IN8, I9 => cnt_val(2), I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_2_D2_PT_4 ); cnt_val_2_D2_PT_5_75 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN0, I1 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN1, I2 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN2, I3 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN3, I4 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN4, I5 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN5, I6 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN6, I7 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN7, I8 => NlwInverterSignal_cnt_val_2_D2_PT_5_IN8, I9 => cnt_val(2), I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_2_D2_PT_5 ); cnt_val_2_D2_76 : X_OR6 port map ( I0 => cnt_val_2_D2_PT_0, I1 => cnt_val_2_D2_PT_1, I2 => cnt_val_2_D2_PT_2, I3 => cnt_val_2_D2_PT_3, I4 => cnt_val_2_D2_PT_4, I5 => cnt_val_2_D2_PT_5, O => cnt_val_2_D2 ); cnt_val_2_RSTF_77 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_2_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_2_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_2_RSTF_IN2, O => cnt_val_2_RSTF ); cnt_val_3_Q_78 : X_BUF port map ( I => cnt_val_3_Q, O => cnt_val(3) ); cnt_val_3_EXP_79 : X_BUF port map ( I => cnt_val_3_EXP_tsimrenamed_net_Q, O => cnt_val_3_EXP ); cnt_val_3_REG : X_FF port map ( I => cnt_val_3_D, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_3_RSTF, O => cnt_val_3_Q ); cnt_val_3_D_80 : X_XOR2 port map ( I0 => cnt_val_3_D1, I1 => cnt_val_3_D2, O => cnt_val_3_D ); cnt_val_3_D1_81 : X_ZERO port map ( O => cnt_val_3_D1 ); cnt_val_3_D2_PT_0_82 : X_AND2 port map ( I0 => EXP11_EXP, I1 => EXP11_EXP, O => cnt_val_3_D2_PT_0 ); cnt_val_3_D2_PT_1_83 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN0, I1 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN1, I2 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN2, I3 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN3, I4 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN4, I5 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN5, I6 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN6, I7 => NlwInverterSignal_cnt_val_3_D2_PT_1_IN7, I8 => cnt_val(3), I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_3_D2_PT_1 ); cnt_val_3_D2_PT_2_84 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN0, I1 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN1, I2 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN2, I3 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN3, I4 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN4, I5 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN5, I6 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN6, I7 => NlwInverterSignal_cnt_val_3_D2_PT_2_IN7, I8 => cnt_val(3), I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_3_D2_PT_2 ); cnt_val_3_D2_85 : X_OR3 port map ( I0 => cnt_val_3_D2_PT_0, I1 => cnt_val_3_D2_PT_1, I2 => cnt_val_3_D2_PT_2, O => cnt_val_3_D2 ); cnt_val_3_RSTF_86 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_3_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_3_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_3_RSTF_IN2, O => cnt_val_3_RSTF ); cnt_val_3_EXP_PT_0_87 : X_AND2 port map ( I0 => NlwInverterSignal_cnt_val_3_EXP_PT_0_IN0, I1 => cnt_val(2), O => cnt_val_3_EXP_PT_0 ); cnt_val_3_EXP_PT_1_88 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_val(2), O => cnt_val_3_EXP_PT_1 ); cnt_val_3_EXP_tsimrenamed_net_Q_89 : X_OR2 port map ( I0 => cnt_val_3_EXP_PT_0, I1 => cnt_val_3_EXP_PT_1, O => cnt_val_3_EXP_tsimrenamed_net_Q ); Inst_ren_wen_Inst_decim_cnt_1_Q_90 : X_BUF port map ( I => Inst_ren_wen_Inst_decim_cnt_1_Q, O => Inst_ren_wen_Inst_decim_cnt(1) ); Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q_91 : X_XOR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_1_D, I1 => Inst_ren_wen_Inst_decim_cnt_1_Q, O => Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q ); Inst_ren_wen_Inst_decim_cnt_1_REG : X_FF port map ( I => Inst_ren_wen_Inst_decim_cnt_1_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => FSR_IO_1, O => Inst_ren_wen_Inst_decim_cnt_1_Q ); Inst_ren_wen_Inst_decim_cnt_1_D_92 : X_XOR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_1_D1, I1 => Inst_ren_wen_Inst_decim_cnt_1_D2, O => Inst_ren_wen_Inst_decim_cnt_1_D ); Inst_ren_wen_Inst_decim_cnt_1_D1_93 : X_ZERO port map ( O => Inst_ren_wen_Inst_decim_cnt_1_D1 ); Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0_94 : X_AND3 port map ( I0 => state_FFT3, I1 => state_FFT1, I2 => Inst_ren_wen_Inst_decim_cnt(0), O => Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0 ); Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_95 : X_AND3 port map ( I0 => state_FFT2, I1 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_IN1, I2 => Inst_ren_wen_Inst_decim_cnt(0), O => Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1 ); Inst_ren_wen_Inst_decim_cnt_1_D2_96 : X_OR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_1_D2_PT_0, I1 => Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1, O => Inst_ren_wen_Inst_decim_cnt_1_D2 ); cnt_val_10_Q_97 : X_BUF port map ( I => cnt_val_10_Q, O => cnt_val(10) ); cnt_val_10_tsimcreated_xor_Q_98 : X_XOR2 port map ( I0 => cnt_val_10_D, I1 => cnt_val_10_Q, O => cnt_val_10_tsimcreated_xor_Q ); cnt_val_10_REG : X_FF port map ( I => cnt_val_10_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_10_RSTF, O => cnt_val_10_Q ); cnt_val_10_D_99 : X_XOR2 port map ( I0 => cnt_val_10_D1, I1 => cnt_val_10_D2, O => cnt_val_10_D ); cnt_val_10_D1_100 : X_ZERO port map ( O => cnt_val_10_D1 ); cnt_val_10_D2_PT_0_101 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_10_D2_PT_0_IN2, I3 => cnt_val(10), O => cnt_val_10_D2_PT_0 ); cnt_val_10_D2_PT_1_102 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_10_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(10), O => cnt_val_10_D2_PT_1 ); cnt_val_10_D2_103 : X_OR2 port map ( I0 => cnt_val_10_D2_PT_0, I1 => cnt_val_10_D2_PT_1, O => cnt_val_10_D2 ); cnt_val_10_RSTF_104 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_10_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_10_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_10_RSTF_IN2, O => cnt_val_10_RSTF ); cnt_val_5_Q_105 : X_BUF port map ( I => cnt_val_5_Q, O => cnt_val(5) ); cnt_val_5_REG : X_FF port map ( I => cnt_val_5_D, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_5_RSTF, O => cnt_val_5_Q ); cnt_val_5_D_106 : X_XOR2 port map ( I0 => cnt_val_5_D1, I1 => cnt_val_5_D2, O => cnt_val_5_D ); cnt_val_5_D1_107 : X_ZERO port map ( O => cnt_val_5_D1 ); cnt_val_5_D2_PT_0_108 : X_AND2 port map ( I0 => EXP7_EXP, I1 => EXP7_EXP, O => cnt_val_5_D2_PT_0 ); cnt_val_5_D2_PT_1_109 : X_AND2 port map ( I0 => NlwInverterSignal_cnt_val_5_D2_PT_1_IN0, I1 => cnt_val(5), O => cnt_val_5_D2_PT_1 ); cnt_val_5_D2_PT_2_110 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_val(5), O => cnt_val_5_D2_PT_2 ); cnt_val_5_D2_PT_3_111 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_5_D2_PT_3_IN0, I1 => NlwInverterSignal_cnt_val_5_D2_PT_3_IN1, I2 => cnt_val(5), O => cnt_val_5_D2_PT_3 ); cnt_val_5_D2_PT_4_112 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN0, I1 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN1, I2 => cnt_val(5), I3 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN3, I4 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN4, I5 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN5, I6 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN6, I7 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN7, I8 => NlwInverterSignal_cnt_val_5_D2_PT_4_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_val_5_D2_PT_4 ); cnt_val_5_D2_113 : X_OR5 port map ( I0 => cnt_val_5_D2_PT_0, I1 => cnt_val_5_D2_PT_1, I2 => cnt_val_5_D2_PT_2, I3 => cnt_val_5_D2_PT_3, I4 => cnt_val_5_D2_PT_4, O => cnt_val_5_D2 ); cnt_val_5_RSTF_114 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_5_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_5_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_5_RSTF_IN2, O => cnt_val_5_RSTF ); cnt_val_6_Q_115 : X_BUF port map ( I => cnt_val_6_Q, O => cnt_val(6) ); cnt_val_6_tsimcreated_xor_Q_116 : X_XOR2 port map ( I0 => cnt_val_6_D, I1 => cnt_val_6_Q, O => cnt_val_6_tsimcreated_xor_Q ); cnt_val_6_REG : X_FF port map ( I => cnt_val_6_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_6_RSTF, O => cnt_val_6_Q ); cnt_val_6_D_117 : X_XOR2 port map ( I0 => cnt_val_6_D1, I1 => cnt_val_6_D2, O => cnt_val_6_D ); cnt_val_6_D1_118 : X_ZERO port map ( O => cnt_val_6_D1 ); cnt_val_6_D2_PT_0_119 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_6_D2_PT_0_IN2, I3 => cnt_val(6), O => cnt_val_6_D2_PT_0 ); cnt_val_6_D2_PT_1_120 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_6_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(6), O => cnt_val_6_D2_PT_1 ); cnt_val_6_D2_121 : X_OR2 port map ( I0 => cnt_val_6_D2_PT_0, I1 => cnt_val_6_D2_PT_1, O => cnt_val_6_D2 ); cnt_val_6_RSTF_122 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_6_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_6_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_6_RSTF_IN2, O => cnt_val_6_RSTF ); cnt_val_7_Q_123 : X_BUF port map ( I => cnt_val_7_Q, O => cnt_val(7) ); cnt_val_7_tsimcreated_xor_Q_124 : X_XOR2 port map ( I0 => cnt_val_7_D, I1 => cnt_val_7_Q, O => cnt_val_7_tsimcreated_xor_Q ); cnt_val_7_REG : X_FF port map ( I => cnt_val_7_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_7_RSTF, O => cnt_val_7_Q ); cnt_val_7_D_125 : X_XOR2 port map ( I0 => cnt_val_7_D1, I1 => cnt_val_7_D2, O => cnt_val_7_D ); cnt_val_7_D1_126 : X_ZERO port map ( O => cnt_val_7_D1 ); cnt_val_7_D2_PT_0_127 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_7_D2_PT_0_IN2, I3 => cnt_val(7), O => cnt_val_7_D2_PT_0 ); cnt_val_7_D2_PT_1_128 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_7_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(7), O => cnt_val_7_D2_PT_1 ); cnt_val_7_D2_129 : X_OR2 port map ( I0 => cnt_val_7_D2_PT_0, I1 => cnt_val_7_D2_PT_1, O => cnt_val_7_D2 ); cnt_val_7_RSTF_130 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_7_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_7_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_7_RSTF_IN2, O => cnt_val_7_RSTF ); cnt_val_8_Q_131 : X_BUF port map ( I => cnt_val_8_Q, O => cnt_val(8) ); cnt_val_8_tsimcreated_xor_Q_132 : X_XOR2 port map ( I0 => cnt_val_8_D, I1 => cnt_val_8_Q, O => cnt_val_8_tsimcreated_xor_Q ); cnt_val_8_REG : X_FF port map ( I => cnt_val_8_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_8_RSTF, O => cnt_val_8_Q ); cnt_val_8_D_133 : X_XOR2 port map ( I0 => cnt_val_8_D1, I1 => cnt_val_8_D2, O => cnt_val_8_D ); cnt_val_8_D1_134 : X_ZERO port map ( O => cnt_val_8_D1 ); cnt_val_8_D2_PT_0_135 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_8_D2_PT_0_IN2, I3 => cnt_val(8), O => cnt_val_8_D2_PT_0 ); cnt_val_8_D2_PT_1_136 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_8_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(8), O => cnt_val_8_D2_PT_1 ); cnt_val_8_D2_137 : X_OR2 port map ( I0 => cnt_val_8_D2_PT_0, I1 => cnt_val_8_D2_PT_1, O => cnt_val_8_D2 ); cnt_val_8_RSTF_138 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_8_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_8_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_8_RSTF_IN2, O => cnt_val_8_RSTF ); cnt_val_9_Q_139 : X_BUF port map ( I => cnt_val_9_Q, O => cnt_val(9) ); cnt_val_9_tsimcreated_xor_Q_140 : X_XOR2 port map ( I0 => cnt_val_9_D, I1 => cnt_val_9_Q, O => cnt_val_9_tsimcreated_xor_Q ); cnt_val_9_REG : X_FF port map ( I => cnt_val_9_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_9_RSTF, O => cnt_val_9_Q ); cnt_val_9_D_141 : X_XOR2 port map ( I0 => cnt_val_9_D1, I1 => cnt_val_9_D2, O => cnt_val_9_D ); cnt_val_9_D1_142 : X_ZERO port map ( O => cnt_val_9_D1 ); cnt_val_9_D2_PT_0_143 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_9_D2_PT_0_IN2, I3 => cnt_val(9), O => cnt_val_9_D2_PT_0 ); cnt_val_9_D2_PT_1_144 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_9_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(9), O => cnt_val_9_D2_PT_1 ); cnt_val_9_D2_145 : X_OR2 port map ( I0 => cnt_val_9_D2_PT_0, I1 => cnt_val_9_D2_PT_1, O => cnt_val_9_D2 ); cnt_val_9_RSTF_146 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_9_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_9_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_9_RSTF_IN2, O => cnt_val_9_RSTF ); Inst_ren_wen_Inst_decim_cnt_2_Q_147 : X_BUF port map ( I => Inst_ren_wen_Inst_decim_cnt_2_Q, O => Inst_ren_wen_Inst_decim_cnt(2) ); Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q_148 : X_XOR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_2_D, I1 => Inst_ren_wen_Inst_decim_cnt_2_Q, O => Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q ); Inst_ren_wen_Inst_decim_cnt_2_REG : X_FF port map ( I => Inst_ren_wen_Inst_decim_cnt_2_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => FSR_IO_1, O => Inst_ren_wen_Inst_decim_cnt_2_Q ); Inst_ren_wen_Inst_decim_cnt_2_D_149 : X_XOR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_2_D1, I1 => Inst_ren_wen_Inst_decim_cnt_2_D2, O => Inst_ren_wen_Inst_decim_cnt_2_D ); Inst_ren_wen_Inst_decim_cnt_2_D1_150 : X_ZERO port map ( O => Inst_ren_wen_Inst_decim_cnt_2_D1 ); Inst_ren_wen_Inst_decim_cnt_2_D2_PT_0_151 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT1, I2 => Inst_ren_wen_Inst_decim_cnt(0), I3 => Inst_ren_wen_Inst_decim_cnt(1), O => Inst_ren_wen_Inst_decim_cnt_2_D2_PT_0 ); Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1_152 : X_AND4 port map ( I0 => state_FFT2, I1 => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1_IN1, I2 => Inst_ren_wen_Inst_decim_cnt(0), I3 => Inst_ren_wen_Inst_decim_cnt(1), O => Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1 ); Inst_ren_wen_Inst_decim_cnt_2_D2_153 : X_OR2 port map ( I0 => Inst_ren_wen_Inst_decim_cnt_2_D2_PT_0, I1 => Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1, O => Inst_ren_wen_Inst_decim_cnt_2_D2 ); cnt_val_11_Q_154 : X_BUF port map ( I => cnt_val_11_Q, O => cnt_val(11) ); cnt_val_11_tsimcreated_xor_Q_155 : X_XOR2 port map ( I0 => cnt_val_11_D, I1 => cnt_val_11_Q, O => cnt_val_11_tsimcreated_xor_Q ); cnt_val_11_REG : X_FF port map ( I => cnt_val_11_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => PRLD, RST => cnt_val_11_RSTF, O => cnt_val_11_Q ); cnt_val_11_D_156 : X_XOR2 port map ( I0 => cnt_val_11_D1, I1 => cnt_val_11_D2, O => cnt_val_11_D ); cnt_val_11_D1_157 : X_ZERO port map ( O => cnt_val_11_D1 ); cnt_val_11_D2_PT_0_158 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_val_11_D2_PT_0_IN2, I3 => cnt_val(11), O => cnt_val_11_D2_PT_0 ); cnt_val_11_D2_PT_1_159 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_val_11_D2_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(11), O => cnt_val_11_D2_PT_1 ); cnt_val_11_D2_160 : X_OR2 port map ( I0 => cnt_val_11_D2_PT_0, I1 => cnt_val_11_D2_PT_1, O => cnt_val_11_D2 ); cnt_val_11_RSTF_161 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_val_11_RSTF_IN0, I1 => NlwInverterSignal_cnt_val_11_RSTF_IN1, I2 => NlwInverterSignal_cnt_val_11_RSTF_IN2, O => cnt_val_11_RSTF ); cnt_ovf1_162 : X_BUF port map ( I => cnt_ovf1_Q, O => cnt_ovf1 ); cnt_ovf1_REG : X_FF port map ( I => cnt_ovf1_D, CE => Vcc, CLK => FCLKIO_0, SET => cnt_ovf1_SETF, RST => PRLD, O => cnt_ovf1_Q ); cnt_ovf1_D_163 : X_XOR2 port map ( I0 => cnt_ovf1_D1, I1 => cnt_ovf1_D2, O => cnt_ovf1_D ); cnt_ovf1_D1_164 : X_ZERO port map ( O => cnt_ovf1_D1 ); cnt_ovf1_D2_PT_0_165 : X_AND2 port map ( I0 => rst2_OBUF_EXP, I1 => rst2_OBUF_EXP, O => cnt_ovf1_D2_PT_0 ); cnt_ovf1_D2_PT_1_166 : X_AND2 port map ( I0 => EXP14_EXP, I1 => EXP14_EXP, O => cnt_ovf1_D2_PT_1 ); cnt_ovf1_D2_PT_2_167 : X_AND2 port map ( I0 => NlwInverterSignal_cnt_ovf1_D2_PT_2_IN0, I1 => cnt_ovf1, O => cnt_ovf1_D2_PT_2 ); cnt_ovf1_D2_PT_3_168 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_ovf1, O => cnt_ovf1_D2_PT_3 ); cnt_ovf1_D2_PT_4_169 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_ovf1_D2_PT_4_IN0, I1 => NlwInverterSignal_cnt_ovf1_D2_PT_4_IN1, I2 => cnt_ovf1, O => cnt_ovf1_D2_PT_4 ); cnt_ovf1_D2_PT_5_170 : X_AND16 port map ( I0 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN4, I5 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN5, I6 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN6, I7 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN7, I8 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN8, I9 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN9, I10 => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN10, I11 => n1param_1_IBUF, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_ovf1_D2_PT_5 ); cnt_ovf1_D2_171 : X_OR6 port map ( I0 => cnt_ovf1_D2_PT_0, I1 => cnt_ovf1_D2_PT_1, I2 => cnt_ovf1_D2_PT_2, I3 => cnt_ovf1_D2_PT_3, I4 => cnt_ovf1_D2_PT_4, I5 => cnt_ovf1_D2_PT_5, O => cnt_ovf1_D2 ); cnt_ovf1_SETF_172 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_ovf1_SETF_IN0, I1 => NlwInverterSignal_cnt_ovf1_SETF_IN1, I2 => NlwInverterSignal_cnt_ovf1_SETF_IN2, O => cnt_ovf1_SETF ); state_FFT2_173 : X_BUF port map ( I => state_FFT2_Q, O => state_FFT2 ); state_FFT2_tsimcreated_xor_Q_174 : X_XOR2 port map ( I0 => state_FFT2_D, I1 => state_FFT2_Q, O => state_FFT2_tsimcreated_xor_Q ); state_FFT2_tsimcreated_prld_Q_175 : X_OR2 port map ( I0 => FSR_IO_1, I1 => PRLD, O => state_FFT2_tsimcreated_prld_Q ); state_FFT2_REG : X_FF port map ( I => state_FFT2_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => Gnd, RST => state_FFT2_tsimcreated_prld_Q, O => state_FFT2_Q ); Gnd_176 : X_ZERO port map ( O => Gnd ); state_FFT2_D_177 : X_XOR2 port map ( I0 => state_FFT2_D1, I1 => state_FFT2_D2, O => state_FFT2_D ); state_FFT2_D1_178 : X_ZERO port map ( O => state_FFT2_D1 ); state_FFT2_D2_PT_0_179 : X_AND4 port map ( I0 => acqen_IBUF, I1 => NlwInverterSignal_state_FFT2_D2_PT_0_IN1, I2 => state_FFT2, I3 => state_FFT1, O => state_FFT2_D2_PT_0 ); state_FFT2_D2_PT_1_180 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, I3 => trigger_IBUF, O => state_FFT2_D2_PT_1 ); state_FFT2_D2_PT_2_181 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_state_FFT2_D2_PT_2_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_state_FFT2_D2_PT_2_IN3, O => state_FFT2_D2_PT_2 ); state_FFT2_D2_PT_3_182 : X_AND4 port map ( I0 => NlwInverterSignal_state_FFT2_D2_PT_3_IN0, I1 => NlwInverterSignal_state_FFT2_D2_PT_3_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_state_FFT2_D2_PT_3_IN3, O => state_FFT2_D2_PT_3 ); state_FFT2_D2_PT_4_183 : X_AND5 port map ( I0 => NlwInverterSignal_state_FFT2_D2_PT_4_IN0, I1 => NlwInverterSignal_state_FFT2_D2_PT_4_IN1, I2 => NlwInverterSignal_state_FFT2_D2_PT_4_IN2, I3 => NlwInverterSignal_state_FFT2_D2_PT_4_IN3, I4 => NlwInverterSignal_state_FFT2_D2_PT_4_IN4, O => state_FFT2_D2_PT_4 ); state_FFT2_D2_184 : X_OR5 port map ( I0 => state_FFT2_D2_PT_0, I1 => state_FFT2_D2_PT_1, I2 => state_FFT2_D2_PT_2, I3 => state_FFT2_D2_PT_3, I4 => state_FFT2_D2_PT_4, O => state_FFT2_D2 ); state_FFT1_185 : X_BUF port map ( I => state_FFT1_Q, O => state_FFT1 ); state_FFT1_tsimcreated_xor_Q_186 : X_XOR2 port map ( I0 => state_FFT1_D, I1 => state_FFT1_Q, O => state_FFT1_tsimcreated_xor_Q ); state_FFT1_tsimcreated_prld_Q_187 : X_OR2 port map ( I0 => FSR_IO_1, I1 => PRLD, O => state_FFT1_tsimcreated_prld_Q ); state_FFT1_REG : X_FF port map ( I => state_FFT1_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => Gnd, RST => state_FFT1_tsimcreated_prld_Q, O => state_FFT1_Q ); state_FFT1_D_188 : X_XOR2 port map ( I0 => state_FFT1_D1, I1 => state_FFT1_D2, O => state_FFT1_D ); state_FFT1_D1_189 : X_ZERO port map ( O => state_FFT1_D1 ); state_FFT1_D2_PT_0_190 : X_AND4 port map ( I0 => acqen_IBUF, I1 => NlwInverterSignal_state_FFT1_D2_PT_0_IN1, I2 => state_FFT2, I3 => state_FFT1, O => state_FFT1_D2_PT_0 ); state_FFT1_D2_PT_1_191 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_state_FFT1_D2_PT_1_IN2, I3 => NlwInverterSignal_state_FFT1_D2_PT_1_IN3, O => state_FFT1_D2_PT_1 ); state_FFT1_D2_PT_2_192 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_state_FFT1_D2_PT_2_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_state_FFT1_D2_PT_2_IN3, O => state_FFT1_D2_PT_2 ); state_FFT1_D2_PT_3_193 : X_AND5 port map ( I0 => trig_mode_IBUF, I1 => NlwInverterSignal_state_FFT1_D2_PT_3_IN1, I2 => NlwInverterSignal_state_FFT1_D2_PT_3_IN2, I3 => NlwInverterSignal_state_FFT1_D2_PT_3_IN3, I4 => NlwInverterSignal_state_FFT1_D2_PT_3_IN4, O => state_FFT1_D2_PT_3 ); state_FFT1_D2_194 : X_OR4 port map ( I0 => state_FFT1_D2_PT_0, I1 => state_FFT1_D2_PT_1, I2 => state_FFT1_D2_PT_2, I3 => state_FFT1_D2_PT_3, O => state_FFT1_D2 ); state_FFT3_195 : X_BUF port map ( I => state_FFT3_Q, O => state_FFT3 ); state_FFT3_tsimcreated_xor_Q_196 : X_XOR2 port map ( I0 => state_FFT3_D, I1 => state_FFT3_Q, O => state_FFT3_tsimcreated_xor_Q ); state_FFT3_tsimcreated_prld_Q_197 : X_OR2 port map ( I0 => FSR_IO_1, I1 => PRLD, O => state_FFT3_tsimcreated_prld_Q ); state_FFT3_REG : X_FF port map ( I => state_FFT3_tsimcreated_xor_Q, CE => Vcc, CLK => FCLKIO_0, SET => Gnd, RST => state_FFT3_tsimcreated_prld_Q, O => state_FFT3_Q ); state_FFT3_D_198 : X_XOR2 port map ( I0 => state_FFT3_D1, I1 => state_FFT3_D2, O => state_FFT3_D ); state_FFT3_D1_199 : X_ZERO port map ( O => state_FFT3_D1 ); state_FFT3_D2_200 : X_AND4 port map ( I0 => NlwInverterSignal_state_FFT3_D2_IN0, I1 => state_FFT2, I2 => NlwInverterSignal_state_FFT3_D2_IN2, I3 => NlwInverterSignal_state_FFT3_D2_IN3, O => state_FFT3_D2 ); cnt_ovf2_201 : X_BUF port map ( I => cnt_ovf2_Q, O => cnt_ovf2 ); cnt_ovf2_REG : X_FF port map ( I => cnt_ovf2_D, CE => Vcc, CLK => FCLKIO_0, SET => Gnd, RST => PRLD, O => cnt_ovf2_Q ); cnt_ovf2_D_202 : X_XOR2 port map ( I0 => cnt_ovf2_D1, I1 => cnt_ovf2_D2, O => cnt_ovf2_D ); cnt_ovf2_D1_203 : X_ZERO port map ( O => cnt_ovf2_D1 ); cnt_ovf2_D2_PT_0_204 : X_AND2 port map ( I0 => EXP15_EXP, I1 => EXP15_EXP, O => cnt_ovf2_D2_PT_0 ); cnt_ovf2_D2_PT_1_205 : X_AND2 port map ( I0 => NlwInverterSignal_cnt_ovf2_D2_PT_1_IN0, I1 => cnt_ovf2, O => cnt_ovf2_D2_PT_1 ); cnt_ovf2_D2_PT_2_206 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_ovf2, O => cnt_ovf2_D2_PT_2 ); cnt_ovf2_D2_PT_3_207 : X_AND3 port map ( I0 => NlwInverterSignal_cnt_ovf2_D2_PT_3_IN0, I1 => NlwInverterSignal_cnt_ovf2_D2_PT_3_IN1, I2 => cnt_ovf2, O => cnt_ovf2_D2_PT_3 ); cnt_ovf2_D2_PT_4_208 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN2, I3 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN3, I4 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN4, I5 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN5, I6 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN6, I7 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN7, I8 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN8, I9 => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN9, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_ovf2_D2_PT_4 ); cnt_ovf2_D2_PT_5_209 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN3, I4 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN4, I5 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN5, I6 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN6, I7 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN7, I8 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN8, I9 => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN9, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => cnt_ovf2_D2_PT_5 ); cnt_ovf2_D2_210 : X_OR6 port map ( I0 => cnt_ovf2_D2_PT_0, I1 => cnt_ovf2_D2_PT_1, I2 => cnt_ovf2_D2_PT_2, I3 => cnt_ovf2_D2_PT_3, I4 => cnt_ovf2_D2_PT_4, I5 => cnt_ovf2_D2_PT_5, O => cnt_ovf2_D2 ); decim_flag_OBUF_Q_211 : X_BUF port map ( I => decim_flag_OBUF_Q_0, O => decim_flag_OBUF_Q ); decim_flag_OBUF_Q_212 : X_BUF port map ( I => decim_flag_OBUF_D, O => decim_flag_OBUF_Q_0 ); decim_flag_OBUF_D_213 : X_XOR2 port map ( I0 => decim_flag_OBUF_D1, I1 => decim_flag_OBUF_D2, O => decim_flag_OBUF_D ); decim_flag_OBUF_D1_214 : X_ZERO port map ( O => decim_flag_OBUF_D1 ); decim_flag_OBUF_D2_PT_0_215 : X_AND2 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_decim_flag_OBUF_D2_PT_0_IN1, O => decim_flag_OBUF_D2_PT_0 ); decim_flag_OBUF_D2_PT_1_216 : X_AND2 port map ( I0 => NlwInverterSignal_decim_flag_OBUF_D2_PT_1_IN0, I1 => state_FFT1, O => decim_flag_OBUF_D2_PT_1 ); decim_flag_OBUF_D2_217 : X_OR2 port map ( I0 => decim_flag_OBUF_D2_PT_0, I1 => decim_flag_OBUF_D2_PT_1, O => decim_flag_OBUF_D2 ); fsmst_0_218 : X_BUF port map ( I => fsmst_0_Q, O => fsmst_0 ); fsmst_0_tsimcreated_set_and_noreset_Q_219 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_0_tsimcreated_set_and_noreset_IN0, I1 => fsmst_0_SETF, O => fsmst_0_tsimcreated_set_and_noreset_Q ); fsmst_0_tsimcreated_prld_Q_220 : X_OR2 port map ( I0 => fsmst_0_RSTF, I1 => PRLD, O => fsmst_0_tsimcreated_prld_Q ); fsmst_0_REG : X_FF port map ( I => fsmst_0_D, CE => Vcc, CLK => fsmst_0_CLKF, SET => fsmst_0_tsimcreated_set_and_noreset_Q, RST => fsmst_0_tsimcreated_prld_Q, O => fsmst_0_Q ); fsmst_0_D_221 : X_XOR2 port map ( I0 => fsmst_0_D1, I1 => fsmst_0_D2, O => fsmst_0_D ); fsmst_0_D1_222 : X_ZERO port map ( O => fsmst_0_D1 ); fsmst_0_D2_223 : X_ZERO port map ( O => fsmst_0_D2 ); fsmst_0_CLKF_224 : X_ZERO port map ( O => fsmst_0_CLKF ); fsmst_0_SETF_225 : X_AND2 port map ( I0 => fsmst_0_fsmst_0_SETF_UIM, I1 => fsmst_0_fsmst_0_SETF_UIM, O => fsmst_0_SETF ); fsmst_0_RSTF_226 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_0_RSTF_IN0, I1 => NlwInverterSignal_fsmst_0_RSTF_IN1, O => fsmst_0_RSTF ); fsmst_1_227 : X_BUF port map ( I => fsmst_1_Q, O => fsmst_1 ); fsmst_1_tsimcreated_set_and_noreset_Q_228 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_1_tsimcreated_set_and_noreset_IN0, I1 => fsmst_1_SETF, O => fsmst_1_tsimcreated_set_and_noreset_Q ); fsmst_1_tsimcreated_prld_Q_229 : X_OR2 port map ( I0 => fsmst_1_RSTF, I1 => PRLD, O => fsmst_1_tsimcreated_prld_Q ); fsmst_1_REG : X_FF port map ( I => fsmst_1_D, CE => Vcc, CLK => fsmst_1_CLKF, SET => fsmst_1_tsimcreated_set_and_noreset_Q, RST => fsmst_1_tsimcreated_prld_Q, O => fsmst_1_Q ); fsmst_1_D_230 : X_XOR2 port map ( I0 => fsmst_1_D1, I1 => fsmst_1_D2, O => fsmst_1_D ); fsmst_1_D1_231 : X_ZERO port map ( O => fsmst_1_D1 ); fsmst_1_D2_232 : X_ZERO port map ( O => fsmst_1_D2 ); fsmst_1_CLKF_233 : X_ZERO port map ( O => fsmst_1_CLKF ); fsmst_1_SETF_234 : X_AND2 port map ( I0 => fsmst_1_fsmst_1_SETF_UIM, I1 => fsmst_1_fsmst_1_SETF_UIM, O => fsmst_1_SETF ); fsmst_1_RSTF_235 : X_AND2 port map ( I0 => fsmst_1_fsmst_1_RSTF_UIM, I1 => fsmst_1_fsmst_1_RSTF_UIM, O => fsmst_1_RSTF ); fsmst_2_236 : X_BUF port map ( I => fsmst_2_Q, O => fsmst_2 ); fsmst_2_tsimcreated_set_and_noreset_Q_237 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_2_tsimcreated_set_and_noreset_IN0, I1 => fsmst_2_SETF, O => fsmst_2_tsimcreated_set_and_noreset_Q ); fsmst_2_tsimcreated_prld_Q_238 : X_OR2 port map ( I0 => fsmst_2_RSTF, I1 => PRLD, O => fsmst_2_tsimcreated_prld_Q ); fsmst_2_REG : X_FF port map ( I => fsmst_2_D, CE => Vcc, CLK => fsmst_2_CLKF, SET => fsmst_2_tsimcreated_set_and_noreset_Q, RST => fsmst_2_tsimcreated_prld_Q, O => fsmst_2_Q ); fsmst_2_D_239 : X_XOR2 port map ( I0 => fsmst_2_D1, I1 => fsmst_2_D2, O => fsmst_2_D ); fsmst_2_D1_240 : X_ZERO port map ( O => fsmst_2_D1 ); fsmst_2_D2_241 : X_ZERO port map ( O => fsmst_2_D2 ); fsmst_2_CLKF_242 : X_ZERO port map ( O => fsmst_2_CLKF ); fsmst_2_SETF_243 : X_AND2 port map ( I0 => fsmst_2_fsmst_2_SETF_UIM, I1 => fsmst_2_fsmst_2_SETF_UIM, O => fsmst_2_SETF ); fsmst_2_RSTF_244 : X_AND2 port map ( I0 => fsmst_2_fsmst_2_RSTF_UIM, I1 => fsmst_2_fsmst_2_RSTF_UIM, O => fsmst_2_RSTF ); counten_OBUF_245 : X_BUF port map ( I => counten_OBUF_Q, O => counten_OBUF ); counten_OBUF_Q_246 : X_BUF port map ( I => counten_OBUF_D, O => counten_OBUF_Q ); counten_OBUF_D_247 : X_XOR2 port map ( I0 => NlwInverterSignal_counten_OBUF_D_IN0, I1 => counten_OBUF_D2, O => counten_OBUF_D ); counten_OBUF_D1_248 : X_ZERO port map ( O => counten_OBUF_D1 ); counten_OBUF_D2_PT_0_249 : X_AND3 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_counten_OBUF_D2_PT_0_IN2, O => counten_OBUF_D2_PT_0 ); counten_OBUF_D2_PT_1_250 : X_AND3 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_counten_OBUF_D2_PT_1_IN1, I2 => state_FFT1, O => counten_OBUF_D2_PT_1 ); counten_OBUF_D2_251 : X_OR2 port map ( I0 => counten_OBUF_D2_PT_0, I1 => counten_OBUF_D2_PT_1, O => counten_OBUF_D2 ); ren2_OBUF_252 : X_BUF port map ( I => ren2_OBUF_Q, O => ren2_OBUF ); ren2_OBUF_Q_253 : X_BUF port map ( I => ren2_OBUF_D, O => ren2_OBUF_Q ); ren2_OBUF_D_254 : X_XOR2 port map ( I0 => NlwInverterSignal_ren2_OBUF_D_IN0, I1 => ren2_OBUF_D2, O => ren2_OBUF_D ); ren2_OBUF_D1_255 : X_ZERO port map ( O => ren2_OBUF_D1 ); ren2_OBUF_D2_PT_0_256 : X_AND6 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, I3 => reset_IBUF, I4 => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN4, I5 => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN5, O => ren2_OBUF_D2_PT_0 ); ren2_OBUF_D2_PT_1_257 : X_AND6 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, I3 => reset_IBUF, I4 => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4, I5 => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN5, O => ren2_OBUF_D2_PT_1 ); ren2_OBUF_D2_PT_2_258 : X_AND7 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, I3 => reset_IBUF, I4 => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4, I5 => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN5, I6 => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN6, O => ren2_OBUF_D2_PT_2 ); ren2_OBUF_D2_PT_3_259 : X_AND7 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, I3 => reset_IBUF, I4 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4, I5 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5, I6 => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN6, O => ren2_OBUF_D2_PT_3 ); ren2_OBUF_D2_260 : X_OR4 port map ( I0 => ren2_OBUF_D2_PT_0, I1 => ren2_OBUF_D2_PT_1, I2 => ren2_OBUF_D2_PT_2, I3 => ren2_OBUF_D2_PT_3, O => ren2_OBUF_D2 ); rst2_OBUF_261 : X_BUF port map ( I => rst2_OBUF_Q, O => rst2_OBUF ); rst2_OBUF_EXP_262 : X_BUF port map ( I => rst2_OBUF_EXP_tsimrenamed_net_Q, O => rst2_OBUF_EXP ); rst2_OBUF_Q_263 : X_BUF port map ( I => rst2_OBUF_D, O => rst2_OBUF_Q ); rst2_OBUF_D_264 : X_XOR2 port map ( I0 => NlwInverterSignal_rst2_OBUF_D_IN0, I1 => rst2_OBUF_D2, O => rst2_OBUF_D ); rst2_OBUF_D1_265 : X_ZERO port map ( O => rst2_OBUF_D1 ); rst2_OBUF_D2_266 : X_AND2 port map ( I0 => EXP6_EXP, I1 => EXP6_EXP, O => rst2_OBUF_D2 ); rst2_OBUF_EXP_PT_0_267 : X_AND16 port map ( I0 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN3, I4 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN4, I5 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN5, I6 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN6, I7 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN7, I8 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN8, I9 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN9, I10 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN10, I11 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN11, I12 => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => rst2_OBUF_EXP_PT_0 ); rst2_OBUF_EXP_PT_1_268 : X_AND16 port map ( I0 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN3, I4 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN4, I5 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN5, I6 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN6, I7 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN7, I8 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN8, I9 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN9, I10 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN10, I11 => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN11, I12 => n1param_0_IBUF, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => rst2_OBUF_EXP_PT_1 ); rst2_OBUF_EXP_PT_2_269 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN2, I3 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN3, I4 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN4, I5 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN5, I6 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN6, I7 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN7, I8 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN8, I9 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN9, I10 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN10, I11 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN11, I12 => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN12, I13 => n1param_1_IBUF, I14 => Vcc, I15 => Vcc, O => rst2_OBUF_EXP_PT_2 ); rst2_OBUF_EXP_PT_3_270 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN3, I4 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN4, I5 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN5, I6 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN6, I7 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN7, I8 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN8, I9 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN9, I10 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN10, I11 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN11, I12 => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN12, I13 => n1param_1_IBUF, I14 => Vcc, I15 => Vcc, O => rst2_OBUF_EXP_PT_3 ); rst2_OBUF_EXP_PT_4_271 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN3, I4 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN4, I5 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN5, I6 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN6, I7 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN7, I8 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN8, I9 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN9, I10 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN10, I11 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN11, I12 => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN12, I13 => n1param_1_IBUF, I14 => Vcc, I15 => Vcc, O => rst2_OBUF_EXP_PT_4 ); rst2_OBUF_EXP_tsimrenamed_net_Q_272 : X_OR5 port map ( I0 => rst2_OBUF_EXP_PT_0, I1 => rst2_OBUF_EXP_PT_1, I2 => rst2_OBUF_EXP_PT_2, I3 => rst2_OBUF_EXP_PT_3, I4 => rst2_OBUF_EXP_PT_4, O => rst2_OBUF_EXP_tsimrenamed_net_Q ); trigger_en_OBUF_Q_273 : X_BUF port map ( I => trigger_en_OBUF_Q_1, O => trigger_en_OBUF_Q ); trigger_en_OBUF_Q_274 : X_BUF port map ( I => trigger_en_OBUF_D, O => trigger_en_OBUF_Q_1 ); trigger_en_OBUF_D_275 : X_XOR2 port map ( I0 => NlwInverterSignal_trigger_en_OBUF_D_IN0, I1 => trigger_en_OBUF_D2, O => trigger_en_OBUF_D ); trigger_en_OBUF_D1_276 : X_ZERO port map ( O => trigger_en_OBUF_D1 ); trigger_en_OBUF_D2_277 : X_AND3 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, O => trigger_en_OBUF_D2 ); wen2_OBUF_278 : X_BUF port map ( I => wen2_OBUF_Q, O => wen2_OBUF ); wen2_OBUF_Q_279 : X_BUF port map ( I => wen2_OBUF_D, O => wen2_OBUF_Q ); wen2_OBUF_D_280 : X_XOR2 port map ( I0 => NlwInverterSignal_wen2_OBUF_D_IN0, I1 => wen2_OBUF_D2, O => wen2_OBUF_D ); wen2_OBUF_D1_281 : X_ZERO port map ( O => wen2_OBUF_D1 ); wen2_OBUF_D2_PT_0_282 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_wen2_OBUF_D2_PT_0_IN1, I2 => state_FFT1, I3 => reset_IBUF, O => wen2_OBUF_D2_PT_0 ); wen2_OBUF_D2_PT_1_283 : X_AND5 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => reset_IBUF, I3 => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3, I4 => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN4, O => wen2_OBUF_D2_PT_1 ); wen2_OBUF_D2_PT_2_284 : X_AND5 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => reset_IBUF, I3 => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN3, I4 => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN4, O => wen2_OBUF_D2_PT_2 ); wen2_OBUF_D2_PT_3_285 : X_AND6 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => reset_IBUF, I3 => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3, I4 => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4, I5 => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN5, O => wen2_OBUF_D2_PT_3 ); wen2_OBUF_D2_PT_4_286 : X_AND6 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => reset_IBUF, I3 => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN3, I4 => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN4, I5 => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN5, O => wen2_OBUF_D2_PT_4 ); wen2_OBUF_D2_287 : X_OR5 port map ( I0 => wen2_OBUF_D2_PT_0, I1 => wen2_OBUF_D2_PT_1, I2 => wen2_OBUF_D2_PT_2, I3 => wen2_OBUF_D2_PT_3, I4 => wen2_OBUF_D2_PT_4, O => wen2_OBUF_D2 ); fsmst_0_fsmst_0_SETF_UIM_288 : X_BUF port map ( I => fsmst_0_fsmst_0_SETF_Q, O => fsmst_0_fsmst_0_SETF_UIM ); fsmst_0_fsmst_0_SETF_Q_289 : X_BUF port map ( I => fsmst_0_fsmst_0_SETF_D, O => fsmst_0_fsmst_0_SETF_Q ); fsmst_0_fsmst_0_SETF_D_290 : X_XOR2 port map ( I0 => fsmst_0_fsmst_0_SETF_D1, I1 => fsmst_0_fsmst_0_SETF_D2, O => fsmst_0_fsmst_0_SETF_D ); fsmst_0_fsmst_0_SETF_D1_291 : X_ZERO port map ( O => fsmst_0_fsmst_0_SETF_D1 ); fsmst_0_fsmst_0_SETF_D2_PT_0_292 : X_AND3 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, O => fsmst_0_fsmst_0_SETF_D2_PT_0 ); fsmst_0_fsmst_0_SETF_D2_PT_1_293 : X_AND3 port map ( I0 => NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN0, I1 => state_FFT2, I2 => NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN2, O => fsmst_0_fsmst_0_SETF_D2_PT_1 ); fsmst_0_fsmst_0_SETF_D2_294 : X_OR2 port map ( I0 => fsmst_0_fsmst_0_SETF_D2_PT_0, I1 => fsmst_0_fsmst_0_SETF_D2_PT_1, O => fsmst_0_fsmst_0_SETF_D2 ); fsmst_0_fsmst_0_RSTF_INT_UIM_295 : X_BUF port map ( I => fsmst_0_fsmst_0_RSTF_INT_Q, O => fsmst_0_fsmst_0_RSTF_INT_UIM ); fsmst_0_fsmst_0_RSTF_INT_Q_296 : X_BUF port map ( I => fsmst_0_fsmst_0_RSTF_INT_D, O => fsmst_0_fsmst_0_RSTF_INT_Q ); fsmst_0_fsmst_0_RSTF_INT_D_297 : X_XOR2 port map ( I0 => fsmst_0_fsmst_0_RSTF_INT_D1, I1 => fsmst_0_fsmst_0_RSTF_INT_D2, O => fsmst_0_fsmst_0_RSTF_INT_D ); fsmst_0_fsmst_0_RSTF_INT_D1_298 : X_ZERO port map ( O => fsmst_0_fsmst_0_RSTF_INT_D1 ); fsmst_0_fsmst_0_RSTF_INT_D2_PT_0_299 : X_AND3 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => state_FFT1, O => fsmst_0_fsmst_0_RSTF_INT_D2_PT_0 ); fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_300 : X_AND3 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN1, I2 => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN2, O => fsmst_0_fsmst_0_RSTF_INT_D2_PT_1 ); fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_301 : X_AND3 port map ( I0 => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN0, I1 => state_FFT2, I2 => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN2, O => fsmst_0_fsmst_0_RSTF_INT_D2_PT_2 ); fsmst_0_fsmst_0_RSTF_INT_D2_302 : X_OR3 port map ( I0 => fsmst_0_fsmst_0_RSTF_INT_D2_PT_0, I1 => fsmst_0_fsmst_0_RSTF_INT_D2_PT_1, I2 => fsmst_0_fsmst_0_RSTF_INT_D2_PT_2, O => fsmst_0_fsmst_0_RSTF_INT_D2 ); fsmst_1_fsmst_1_SETF_UIM_303 : X_BUF port map ( I => fsmst_1_fsmst_1_SETF_Q, O => fsmst_1_fsmst_1_SETF_UIM ); fsmst_1_fsmst_1_SETF_Q_304 : X_BUF port map ( I => fsmst_1_fsmst_1_SETF_D, O => fsmst_1_fsmst_1_SETF_Q ); fsmst_1_fsmst_1_SETF_D_305 : X_XOR2 port map ( I0 => fsmst_1_fsmst_1_SETF_D1, I1 => fsmst_1_fsmst_1_SETF_D2, O => fsmst_1_fsmst_1_SETF_D ); fsmst_1_fsmst_1_SETF_D1_306 : X_ZERO port map ( O => fsmst_1_fsmst_1_SETF_D1 ); fsmst_1_fsmst_1_SETF_D2_PT_0_307 : X_AND2 port map ( I0 => state_FFT3, I1 => state_FFT2, O => fsmst_1_fsmst_1_SETF_D2_PT_0 ); fsmst_1_fsmst_1_SETF_D2_PT_1_308 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_1_fsmst_1_SETF_D2_PT_1_IN0, I1 => state_FFT1, O => fsmst_1_fsmst_1_SETF_D2_PT_1 ); fsmst_1_fsmst_1_SETF_D2_309 : X_OR2 port map ( I0 => fsmst_1_fsmst_1_SETF_D2_PT_0, I1 => fsmst_1_fsmst_1_SETF_D2_PT_1, O => fsmst_1_fsmst_1_SETF_D2 ); fsmst_1_fsmst_1_RSTF_UIM_310 : X_BUF port map ( I => fsmst_1_fsmst_1_RSTF_Q, O => fsmst_1_fsmst_1_RSTF_UIM ); fsmst_1_fsmst_1_RSTF_Q_311 : X_BUF port map ( I => fsmst_1_fsmst_1_RSTF_D, O => fsmst_1_fsmst_1_RSTF_Q ); fsmst_1_fsmst_1_RSTF_D_312 : X_XOR2 port map ( I0 => fsmst_1_fsmst_1_RSTF_D1, I1 => fsmst_1_fsmst_1_RSTF_D2, O => fsmst_1_fsmst_1_RSTF_D ); fsmst_1_fsmst_1_RSTF_D1_313 : X_ZERO port map ( O => fsmst_1_fsmst_1_RSTF_D1 ); fsmst_1_fsmst_1_RSTF_D2_PT_0_314 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN0, I1 => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN1, O => fsmst_1_fsmst_1_RSTF_D2_PT_0 ); fsmst_1_fsmst_1_RSTF_D2_PT_1_315 : X_AND3 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_1_IN1, I2 => state_FFT1, O => fsmst_1_fsmst_1_RSTF_D2_PT_1 ); fsmst_1_fsmst_1_RSTF_D2_316 : X_OR2 port map ( I0 => fsmst_1_fsmst_1_RSTF_D2_PT_0, I1 => fsmst_1_fsmst_1_RSTF_D2_PT_1, O => fsmst_1_fsmst_1_RSTF_D2 ); fsmst_2_fsmst_2_SETF_UIM_317 : X_BUF port map ( I => fsmst_2_fsmst_2_SETF_Q, O => fsmst_2_fsmst_2_SETF_UIM ); fsmst_2_fsmst_2_SETF_Q_318 : X_BUF port map ( I => fsmst_2_fsmst_2_SETF_D, O => fsmst_2_fsmst_2_SETF_Q ); fsmst_2_fsmst_2_SETF_D_319 : X_XOR2 port map ( I0 => fsmst_2_fsmst_2_SETF_D1, I1 => fsmst_2_fsmst_2_SETF_D2, O => fsmst_2_fsmst_2_SETF_D ); fsmst_2_fsmst_2_SETF_D1_320 : X_ZERO port map ( O => fsmst_2_fsmst_2_SETF_D1 ); fsmst_2_fsmst_2_SETF_D2_PT_0_321 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_0_IN0, I1 => state_FFT1, O => fsmst_2_fsmst_2_SETF_D2_PT_0 ); fsmst_2_fsmst_2_SETF_D2_PT_1_322 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_1_IN0, I1 => state_FFT1, O => fsmst_2_fsmst_2_SETF_D2_PT_1 ); fsmst_2_fsmst_2_SETF_D2_323 : X_OR2 port map ( I0 => fsmst_2_fsmst_2_SETF_D2_PT_0, I1 => fsmst_2_fsmst_2_SETF_D2_PT_1, O => fsmst_2_fsmst_2_SETF_D2 ); fsmst_2_fsmst_2_RSTF_UIM_324 : X_BUF port map ( I => fsmst_2_fsmst_2_RSTF_Q, O => fsmst_2_fsmst_2_RSTF_UIM ); fsmst_2_fsmst_2_RSTF_Q_325 : X_BUF port map ( I => fsmst_2_fsmst_2_RSTF_D, O => fsmst_2_fsmst_2_RSTF_Q ); fsmst_2_fsmst_2_RSTF_D_326 : X_XOR2 port map ( I0 => fsmst_2_fsmst_2_RSTF_D1, I1 => fsmst_2_fsmst_2_RSTF_D2, O => fsmst_2_fsmst_2_RSTF_D ); fsmst_2_fsmst_2_RSTF_D1_327 : X_ZERO port map ( O => fsmst_2_fsmst_2_RSTF_D1 ); fsmst_2_fsmst_2_RSTF_D2_PT_0_328 : X_AND2 port map ( I0 => state_FFT3, I1 => state_FFT2, O => fsmst_2_fsmst_2_RSTF_D2_PT_0 ); fsmst_2_fsmst_2_RSTF_D2_PT_1_329 : X_AND2 port map ( I0 => NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN0, I1 => NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN1, O => fsmst_2_fsmst_2_RSTF_D2_PT_1 ); fsmst_2_fsmst_2_RSTF_D2_330 : X_OR2 port map ( I0 => fsmst_2_fsmst_2_RSTF_D2_PT_0, I1 => fsmst_2_fsmst_2_RSTF_D2_PT_1, O => fsmst_2_fsmst_2_RSTF_D2 ); EXP6_EXP_331 : X_BUF port map ( I => EXP6_EXP_tsimrenamed_net_Q, O => EXP6_EXP ); EXP6_EXP_tsimrenamed_net_Q_332 : X_AND3 port map ( I0 => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN0, I1 => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN1, I2 => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN2, O => EXP6_EXP_tsimrenamed_net_Q ); EXP7_EXP_333 : X_BUF port map ( I => EXP7_EXP_tsimrenamed_net_Q, O => EXP7_EXP ); EXP7_EXP_PT_0_334 : X_AND16 port map ( I0 => cnt_val(4), I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP7_EXP_PT_0_IN3, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_EXP7_EXP_PT_0_IN6, I7 => NlwInverterSignal_EXP7_EXP_PT_0_IN7, I8 => NlwInverterSignal_EXP7_EXP_PT_0_IN8, I9 => NlwInverterSignal_EXP7_EXP_PT_0_IN9, I10 => NlwInverterSignal_EXP7_EXP_PT_0_IN10, I11 => NlwInverterSignal_EXP7_EXP_PT_0_IN11, I12 => NlwInverterSignal_EXP7_EXP_PT_0_IN12, I13 => cnt_val(3), I14 => cnt_val(2), I15 => Vcc, O => EXP7_EXP_PT_0 ); EXP7_EXP_PT_1_335 : X_AND16 port map ( I0 => cnt_val(4), I1 => state_FFT3, I2 => NlwInverterSignal_EXP7_EXP_PT_1_IN2, I3 => state_FFT1, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_EXP7_EXP_PT_1_IN6, I7 => NlwInverterSignal_EXP7_EXP_PT_1_IN7, I8 => NlwInverterSignal_EXP7_EXP_PT_1_IN8, I9 => NlwInverterSignal_EXP7_EXP_PT_1_IN9, I10 => NlwInverterSignal_EXP7_EXP_PT_1_IN10, I11 => NlwInverterSignal_EXP7_EXP_PT_1_IN11, I12 => NlwInverterSignal_EXP7_EXP_PT_1_IN12, I13 => cnt_val(3), I14 => cnt_val(2), I15 => Vcc, O => EXP7_EXP_PT_1 ); EXP7_EXP_tsimrenamed_net_Q_336 : X_OR2 port map ( I0 => EXP7_EXP_PT_0, I1 => EXP7_EXP_PT_1, O => EXP7_EXP_tsimrenamed_net_Q ); EXP8_EXP_337 : X_BUF port map ( I => EXP8_EXP_tsimrenamed_net_Q, O => EXP8_EXP ); EXP8_EXP_PT_0_338 : X_AND4 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_EXP8_EXP_PT_0_IN2, I3 => cnt_val(0), O => EXP8_EXP_PT_0 ); EXP8_EXP_PT_1_339 : X_AND4 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_EXP8_EXP_PT_1_IN1, I2 => state_FFT1, I3 => cnt_val(0), O => EXP8_EXP_PT_1 ); EXP8_EXP_PT_2_340 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_EXP8_EXP_PT_2_IN2, I3 => NlwInverterSignal_EXP8_EXP_PT_2_IN3, I4 => NlwInverterSignal_EXP8_EXP_PT_2_IN4, I5 => NlwInverterSignal_EXP8_EXP_PT_2_IN5, I6 => NlwInverterSignal_EXP8_EXP_PT_2_IN6, I7 => NlwInverterSignal_EXP8_EXP_PT_2_IN7, I8 => NlwInverterSignal_EXP8_EXP_PT_2_IN8, I9 => NlwInverterSignal_EXP8_EXP_PT_2_IN9, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP8_EXP_PT_2 ); EXP8_EXP_PT_3_341 : X_AND16 port map ( I0 => NlwInverterSignal_EXP8_EXP_PT_3_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP8_EXP_PT_3_IN3, I4 => NlwInverterSignal_EXP8_EXP_PT_3_IN4, I5 => NlwInverterSignal_EXP8_EXP_PT_3_IN5, I6 => NlwInverterSignal_EXP8_EXP_PT_3_IN6, I7 => NlwInverterSignal_EXP8_EXP_PT_3_IN7, I8 => NlwInverterSignal_EXP8_EXP_PT_3_IN8, I9 => NlwInverterSignal_EXP8_EXP_PT_3_IN9, I10 => NlwInverterSignal_EXP8_EXP_PT_3_IN10, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP8_EXP_PT_3 ); EXP8_EXP_PT_4_342 : X_AND16 port map ( I0 => NlwInverterSignal_EXP8_EXP_PT_4_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP8_EXP_PT_4_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP8_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP8_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP8_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP8_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP8_EXP_PT_4_IN8, I9 => NlwInverterSignal_EXP8_EXP_PT_4_IN9, I10 => NlwInverterSignal_EXP8_EXP_PT_4_IN10, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP8_EXP_PT_4 ); EXP8_EXP_tsimrenamed_net_Q_343 : X_OR5 port map ( I0 => EXP8_EXP_PT_0, I1 => EXP8_EXP_PT_1, I2 => EXP8_EXP_PT_2, I3 => EXP8_EXP_PT_3, I4 => EXP8_EXP_PT_4, O => EXP8_EXP_tsimrenamed_net_Q ); EXP9_EXP_344 : X_BUF port map ( I => EXP9_EXP_tsimrenamed_net_Q, O => EXP9_EXP ); EXP9_EXP_PT_0_345 : X_AND2 port map ( I0 => cnt_val_0_EXP, I1 => cnt_val_0_EXP, O => EXP9_EXP_PT_0 ); EXP9_EXP_PT_1_346 : X_AND3 port map ( I0 => cnt_val(4), I1 => state_FFT2, I2 => state_FFT1, O => EXP9_EXP_PT_1 ); EXP9_EXP_PT_2_347 : X_AND3 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_EXP9_EXP_PT_2_IN1, I2 => NlwInverterSignal_EXP9_EXP_PT_2_IN2, O => EXP9_EXP_PT_2 ); EXP9_EXP_PT_3_348 : X_AND16 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_EXP9_EXP_PT_3_IN1, I2 => NlwInverterSignal_EXP9_EXP_PT_3_IN2, I3 => NlwInverterSignal_EXP9_EXP_PT_3_IN3, I4 => NlwInverterSignal_EXP9_EXP_PT_3_IN4, I5 => NlwInverterSignal_EXP9_EXP_PT_3_IN5, I6 => NlwInverterSignal_EXP9_EXP_PT_3_IN6, I7 => NlwInverterSignal_EXP9_EXP_PT_3_IN7, I8 => NlwInverterSignal_EXP9_EXP_PT_3_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP9_EXP_PT_3 ); EXP9_EXP_PT_4_349 : X_AND16 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_EXP9_EXP_PT_4_IN1, I2 => NlwInverterSignal_EXP9_EXP_PT_4_IN2, I3 => NlwInverterSignal_EXP9_EXP_PT_4_IN3, I4 => NlwInverterSignal_EXP9_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP9_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP9_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP9_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP9_EXP_PT_4_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP9_EXP_PT_4 ); EXP9_EXP_PT_5_350 : X_AND16 port map ( I0 => cnt_val(4), I1 => NlwInverterSignal_EXP9_EXP_PT_5_IN1, I2 => NlwInverterSignal_EXP9_EXP_PT_5_IN2, I3 => NlwInverterSignal_EXP9_EXP_PT_5_IN3, I4 => NlwInverterSignal_EXP9_EXP_PT_5_IN4, I5 => NlwInverterSignal_EXP9_EXP_PT_5_IN5, I6 => NlwInverterSignal_EXP9_EXP_PT_5_IN6, I7 => NlwInverterSignal_EXP9_EXP_PT_5_IN7, I8 => NlwInverterSignal_EXP9_EXP_PT_5_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP9_EXP_PT_5 ); EXP9_EXP_tsimrenamed_net_Q_351 : X_OR6 port map ( I0 => EXP9_EXP_PT_0, I1 => EXP9_EXP_PT_1, I2 => EXP9_EXP_PT_2, I3 => EXP9_EXP_PT_3, I4 => EXP9_EXP_PT_4, I5 => EXP9_EXP_PT_5, O => EXP9_EXP_tsimrenamed_net_Q ); EXP10_EXP_352 : X_BUF port map ( I => EXP10_EXP_tsimrenamed_net_Q, O => EXP10_EXP ); EXP10_EXP_PT_0_353 : X_AND2 port map ( I0 => cnt_val_4_EXP, I1 => cnt_val_4_EXP, O => EXP10_EXP_PT_0 ); EXP10_EXP_PT_1_354 : X_AND2 port map ( I0 => NlwInverterSignal_EXP10_EXP_PT_1_IN0, I1 => cnt_val(1), O => EXP10_EXP_PT_1 ); EXP10_EXP_PT_2_355 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_val(1), O => EXP10_EXP_PT_2 ); EXP10_EXP_PT_3_356 : X_AND3 port map ( I0 => NlwInverterSignal_EXP10_EXP_PT_3_IN0, I1 => NlwInverterSignal_EXP10_EXP_PT_3_IN1, I2 => cnt_val(1), O => EXP10_EXP_PT_3 ); EXP10_EXP_PT_4_357 : X_AND16 port map ( I0 => NlwInverterSignal_EXP10_EXP_PT_4_IN0, I1 => cnt_val(1), I2 => NlwInverterSignal_EXP10_EXP_PT_4_IN2, I3 => NlwInverterSignal_EXP10_EXP_PT_4_IN3, I4 => NlwInverterSignal_EXP10_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP10_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP10_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP10_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP10_EXP_PT_4_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP10_EXP_PT_4 ); EXP10_EXP_PT_5_358 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_EXP10_EXP_PT_5_IN1, I2 => state_FFT1, I3 => cnt_val(0), I4 => NlwInverterSignal_EXP10_EXP_PT_5_IN4, I5 => NlwInverterSignal_EXP10_EXP_PT_5_IN5, I6 => NlwInverterSignal_EXP10_EXP_PT_5_IN6, I7 => NlwInverterSignal_EXP10_EXP_PT_5_IN7, I8 => NlwInverterSignal_EXP10_EXP_PT_5_IN8, I9 => NlwInverterSignal_EXP10_EXP_PT_5_IN9, I10 => NlwInverterSignal_EXP10_EXP_PT_5_IN10, I11 => NlwInverterSignal_EXP10_EXP_PT_5_IN11, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP10_EXP_PT_5 ); EXP10_EXP_tsimrenamed_net_Q_359 : X_OR6 port map ( I0 => EXP10_EXP_PT_0, I1 => EXP10_EXP_PT_1, I2 => EXP10_EXP_PT_2, I3 => EXP10_EXP_PT_3, I4 => EXP10_EXP_PT_4, I5 => EXP10_EXP_PT_5, O => EXP10_EXP_tsimrenamed_net_Q ); EXP11_EXP_360 : X_BUF port map ( I => EXP11_EXP_tsimrenamed_net_Q, O => EXP11_EXP ); EXP11_EXP_PT_0_361 : X_AND2 port map ( I0 => cnt_val_1_EXP, I1 => cnt_val_1_EXP, O => EXP11_EXP_PT_0 ); EXP11_EXP_PT_1_362 : X_AND2 port map ( I0 => NlwInverterSignal_EXP11_EXP_PT_1_IN0, I1 => cnt_val(3), O => EXP11_EXP_PT_1 ); EXP11_EXP_PT_2_363 : X_AND3 port map ( I0 => state_FFT2, I1 => state_FFT1, I2 => cnt_val(3), O => EXP11_EXP_PT_2 ); EXP11_EXP_PT_3_364 : X_AND3 port map ( I0 => NlwInverterSignal_EXP11_EXP_PT_3_IN0, I1 => NlwInverterSignal_EXP11_EXP_PT_3_IN1, I2 => cnt_val(3), O => EXP11_EXP_PT_3 ); EXP11_EXP_PT_4_365 : X_AND16 port map ( I0 => NlwInverterSignal_EXP11_EXP_PT_4_IN0, I1 => NlwInverterSignal_EXP11_EXP_PT_4_IN1, I2 => NlwInverterSignal_EXP11_EXP_PT_4_IN2, I3 => NlwInverterSignal_EXP11_EXP_PT_4_IN3, I4 => NlwInverterSignal_EXP11_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP11_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP11_EXP_PT_4_IN6, I7 => cnt_val(3), I8 => NlwInverterSignal_EXP11_EXP_PT_4_IN8, I9 => Vcc, I10 => Vcc, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP11_EXP_PT_4 ); EXP11_EXP_PT_5_366 : X_AND16 port map ( I0 => NlwInverterSignal_EXP11_EXP_PT_5_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP11_EXP_PT_5_IN2, I3 => state_FFT1, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_EXP11_EXP_PT_5_IN6, I7 => NlwInverterSignal_EXP11_EXP_PT_5_IN7, I8 => NlwInverterSignal_EXP11_EXP_PT_5_IN8, I9 => NlwInverterSignal_EXP11_EXP_PT_5_IN9, I10 => NlwInverterSignal_EXP11_EXP_PT_5_IN10, I11 => NlwInverterSignal_EXP11_EXP_PT_5_IN11, I12 => NlwInverterSignal_EXP11_EXP_PT_5_IN12, I13 => cnt_val(2), I14 => Vcc, I15 => Vcc, O => EXP11_EXP_PT_5 ); EXP11_EXP_tsimrenamed_net_Q_367 : X_OR6 port map ( I0 => EXP11_EXP_PT_0, I1 => EXP11_EXP_PT_1, I2 => EXP11_EXP_PT_2, I3 => EXP11_EXP_PT_3, I4 => EXP11_EXP_PT_4, I5 => EXP11_EXP_PT_5, O => EXP11_EXP_tsimrenamed_net_Q ); EXP12_EXP_368 : X_BUF port map ( I => EXP12_EXP_tsimrenamed_net_Q, O => EXP12_EXP ); EXP12_EXP_PT_0_369 : X_AND3 port map ( I0 => NlwInverterSignal_EXP12_EXP_PT_0_IN0, I1 => NlwInverterSignal_EXP12_EXP_PT_0_IN1, I2 => cnt_val(2), O => EXP12_EXP_PT_0 ); EXP12_EXP_PT_1_370 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_EXP12_EXP_PT_1_IN2, I3 => cnt_val(0), I4 => cnt_val(1), I5 => NlwInverterSignal_EXP12_EXP_PT_1_IN5, I6 => NlwInverterSignal_EXP12_EXP_PT_1_IN6, I7 => NlwInverterSignal_EXP12_EXP_PT_1_IN7, I8 => NlwInverterSignal_EXP12_EXP_PT_1_IN8, I9 => NlwInverterSignal_EXP12_EXP_PT_1_IN9, I10 => NlwInverterSignal_EXP12_EXP_PT_1_IN10, I11 => NlwInverterSignal_EXP12_EXP_PT_1_IN11, I12 => NlwInverterSignal_EXP12_EXP_PT_1_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP12_EXP_PT_1 ); EXP12_EXP_PT_2_371 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_EXP12_EXP_PT_2_IN1, I2 => state_FFT1, I3 => cnt_val(0), I4 => cnt_val(1), I5 => NlwInverterSignal_EXP12_EXP_PT_2_IN5, I6 => NlwInverterSignal_EXP12_EXP_PT_2_IN6, I7 => NlwInverterSignal_EXP12_EXP_PT_2_IN7, I8 => NlwInverterSignal_EXP12_EXP_PT_2_IN8, I9 => NlwInverterSignal_EXP12_EXP_PT_2_IN9, I10 => NlwInverterSignal_EXP12_EXP_PT_2_IN10, I11 => NlwInverterSignal_EXP12_EXP_PT_2_IN11, I12 => NlwInverterSignal_EXP12_EXP_PT_2_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP12_EXP_PT_2 ); EXP12_EXP_PT_3_372 : X_AND16 port map ( I0 => NlwInverterSignal_EXP12_EXP_PT_3_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP12_EXP_PT_3_IN3, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_EXP12_EXP_PT_3_IN6, I7 => NlwInverterSignal_EXP12_EXP_PT_3_IN7, I8 => NlwInverterSignal_EXP12_EXP_PT_3_IN8, I9 => NlwInverterSignal_EXP12_EXP_PT_3_IN9, I10 => NlwInverterSignal_EXP12_EXP_PT_3_IN10, I11 => NlwInverterSignal_EXP12_EXP_PT_3_IN11, I12 => NlwInverterSignal_EXP12_EXP_PT_3_IN12, I13 => NlwInverterSignal_EXP12_EXP_PT_3_IN13, I14 => Vcc, I15 => Vcc, O => EXP12_EXP_PT_3 ); EXP12_EXP_PT_4_373 : X_AND16 port map ( I0 => NlwInverterSignal_EXP12_EXP_PT_4_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP12_EXP_PT_4_IN2, I3 => state_FFT1, I4 => cnt_val(0), I5 => cnt_val(1), I6 => NlwInverterSignal_EXP12_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP12_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP12_EXP_PT_4_IN8, I9 => NlwInverterSignal_EXP12_EXP_PT_4_IN9, I10 => NlwInverterSignal_EXP12_EXP_PT_4_IN10, I11 => NlwInverterSignal_EXP12_EXP_PT_4_IN11, I12 => NlwInverterSignal_EXP12_EXP_PT_4_IN12, I13 => NlwInverterSignal_EXP12_EXP_PT_4_IN13, I14 => Vcc, I15 => Vcc, O => EXP12_EXP_PT_4 ); EXP12_EXP_tsimrenamed_net_Q_374 : X_OR5 port map ( I0 => EXP12_EXP_PT_0, I1 => EXP12_EXP_PT_1, I2 => EXP12_EXP_PT_2, I3 => EXP12_EXP_PT_3, I4 => EXP12_EXP_PT_4, O => EXP12_EXP_tsimrenamed_net_Q ); EXP13_EXP_375 : X_BUF port map ( I => EXP13_EXP_tsimrenamed_net_Q, O => EXP13_EXP ); EXP13_EXP_PT_0_376 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_EXP13_EXP_PT_0_IN2, I3 => NlwInverterSignal_EXP13_EXP_PT_0_IN3, I4 => NlwInverterSignal_EXP13_EXP_PT_0_IN4, I5 => NlwInverterSignal_EXP13_EXP_PT_0_IN5, I6 => NlwInverterSignal_EXP13_EXP_PT_0_IN6, I7 => NlwInverterSignal_EXP13_EXP_PT_0_IN7, I8 => NlwInverterSignal_EXP13_EXP_PT_0_IN8, I9 => NlwInverterSignal_EXP13_EXP_PT_0_IN9, I10 => NlwInverterSignal_EXP13_EXP_PT_0_IN10, I11 => NlwInverterSignal_EXP13_EXP_PT_0_IN11, I12 => NlwInverterSignal_EXP13_EXP_PT_0_IN12, I13 => n1param_1_IBUF, I14 => Vcc, I15 => Vcc, O => EXP13_EXP_PT_0 ); EXP13_EXP_PT_1_377 : X_AND16 port map ( I0 => NlwInverterSignal_EXP13_EXP_PT_1_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP13_EXP_PT_1_IN3, I4 => NlwInverterSignal_EXP13_EXP_PT_1_IN4, I5 => NlwInverterSignal_EXP13_EXP_PT_1_IN5, I6 => NlwInverterSignal_EXP13_EXP_PT_1_IN6, I7 => NlwInverterSignal_EXP13_EXP_PT_1_IN7, I8 => NlwInverterSignal_EXP13_EXP_PT_1_IN8, I9 => NlwInverterSignal_EXP13_EXP_PT_1_IN9, I10 => NlwInverterSignal_EXP13_EXP_PT_1_IN10, I11 => NlwInverterSignal_EXP13_EXP_PT_1_IN11, I12 => NlwInverterSignal_EXP13_EXP_PT_1_IN12, I13 => NlwInverterSignal_EXP13_EXP_PT_1_IN13, I14 => n1param_0_IBUF, I15 => Vcc, O => EXP13_EXP_PT_1 ); EXP13_EXP_PT_2_378 : X_AND16 port map ( I0 => NlwInverterSignal_EXP13_EXP_PT_2_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP13_EXP_PT_2_IN3, I4 => NlwInverterSignal_EXP13_EXP_PT_2_IN4, I5 => NlwInverterSignal_EXP13_EXP_PT_2_IN5, I6 => NlwInverterSignal_EXP13_EXP_PT_2_IN6, I7 => NlwInverterSignal_EXP13_EXP_PT_2_IN7, I8 => NlwInverterSignal_EXP13_EXP_PT_2_IN8, I9 => NlwInverterSignal_EXP13_EXP_PT_2_IN9, I10 => NlwInverterSignal_EXP13_EXP_PT_2_IN10, I11 => NlwInverterSignal_EXP13_EXP_PT_2_IN11, I12 => NlwInverterSignal_EXP13_EXP_PT_2_IN12, I13 => n1param_1_IBUF, I14 => n1param_0_IBUF, I15 => Vcc, O => EXP13_EXP_PT_2 ); EXP13_EXP_PT_3_379 : X_AND16 port map ( I0 => NlwInverterSignal_EXP13_EXP_PT_3_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP13_EXP_PT_3_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP13_EXP_PT_3_IN4, I5 => NlwInverterSignal_EXP13_EXP_PT_3_IN5, I6 => NlwInverterSignal_EXP13_EXP_PT_3_IN6, I7 => NlwInverterSignal_EXP13_EXP_PT_3_IN7, I8 => NlwInverterSignal_EXP13_EXP_PT_3_IN8, I9 => NlwInverterSignal_EXP13_EXP_PT_3_IN9, I10 => NlwInverterSignal_EXP13_EXP_PT_3_IN10, I11 => NlwInverterSignal_EXP13_EXP_PT_3_IN11, I12 => NlwInverterSignal_EXP13_EXP_PT_3_IN12, I13 => NlwInverterSignal_EXP13_EXP_PT_3_IN13, I14 => n1param_0_IBUF, I15 => Vcc, O => EXP13_EXP_PT_3 ); EXP13_EXP_PT_4_380 : X_AND16 port map ( I0 => NlwInverterSignal_EXP13_EXP_PT_4_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP13_EXP_PT_4_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP13_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP13_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP13_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP13_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP13_EXP_PT_4_IN8, I9 => NlwInverterSignal_EXP13_EXP_PT_4_IN9, I10 => NlwInverterSignal_EXP13_EXP_PT_4_IN10, I11 => NlwInverterSignal_EXP13_EXP_PT_4_IN11, I12 => NlwInverterSignal_EXP13_EXP_PT_4_IN12, I13 => n1param_1_IBUF, I14 => n1param_0_IBUF, I15 => Vcc, O => EXP13_EXP_PT_4 ); EXP13_EXP_tsimrenamed_net_Q_381 : X_OR5 port map ( I0 => EXP13_EXP_PT_0, I1 => EXP13_EXP_PT_1, I2 => EXP13_EXP_PT_2, I3 => EXP13_EXP_PT_3, I4 => EXP13_EXP_PT_4, O => EXP13_EXP_tsimrenamed_net_Q ); EXP14_EXP_382 : X_BUF port map ( I => EXP14_EXP_tsimrenamed_net_Q, O => EXP14_EXP ); EXP14_EXP_PT_0_383 : X_AND2 port map ( I0 => EXP13_EXP, I1 => EXP13_EXP, O => EXP14_EXP_PT_0 ); EXP14_EXP_PT_1_384 : X_AND16 port map ( I0 => NlwInverterSignal_EXP14_EXP_PT_1_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP14_EXP_PT_1_IN3, I4 => NlwInverterSignal_EXP14_EXP_PT_1_IN4, I5 => NlwInverterSignal_EXP14_EXP_PT_1_IN5, I6 => NlwInverterSignal_EXP14_EXP_PT_1_IN6, I7 => NlwInverterSignal_EXP14_EXP_PT_1_IN7, I8 => NlwInverterSignal_EXP14_EXP_PT_1_IN8, I9 => NlwInverterSignal_EXP14_EXP_PT_1_IN9, I10 => NlwInverterSignal_EXP14_EXP_PT_1_IN10, I11 => n1param_1_IBUF, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP14_EXP_PT_1 ); EXP14_EXP_PT_2_385 : X_AND16 port map ( I0 => state_FFT3, I1 => state_FFT2, I2 => NlwInverterSignal_EXP14_EXP_PT_2_IN2, I3 => NlwInverterSignal_EXP14_EXP_PT_2_IN3, I4 => NlwInverterSignal_EXP14_EXP_PT_2_IN4, I5 => NlwInverterSignal_EXP14_EXP_PT_2_IN5, I6 => NlwInverterSignal_EXP14_EXP_PT_2_IN6, I7 => NlwInverterSignal_EXP14_EXP_PT_2_IN7, I8 => NlwInverterSignal_EXP14_EXP_PT_2_IN8, I9 => NlwInverterSignal_EXP14_EXP_PT_2_IN9, I10 => n1param_1_IBUF, I11 => n1param_0_IBUF, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP14_EXP_PT_2 ); EXP14_EXP_PT_3_386 : X_AND16 port map ( I0 => state_FFT3, I1 => NlwInverterSignal_EXP14_EXP_PT_3_IN1, I2 => state_FFT1, I3 => NlwInverterSignal_EXP14_EXP_PT_3_IN3, I4 => NlwInverterSignal_EXP14_EXP_PT_3_IN4, I5 => NlwInverterSignal_EXP14_EXP_PT_3_IN5, I6 => NlwInverterSignal_EXP14_EXP_PT_3_IN6, I7 => NlwInverterSignal_EXP14_EXP_PT_3_IN7, I8 => NlwInverterSignal_EXP14_EXP_PT_3_IN8, I9 => NlwInverterSignal_EXP14_EXP_PT_3_IN9, I10 => n1param_1_IBUF, I11 => n1param_0_IBUF, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP14_EXP_PT_3 ); EXP14_EXP_PT_4_387 : X_AND16 port map ( I0 => NlwInverterSignal_EXP14_EXP_PT_4_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP14_EXP_PT_4_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP14_EXP_PT_4_IN4, I5 => NlwInverterSignal_EXP14_EXP_PT_4_IN5, I6 => NlwInverterSignal_EXP14_EXP_PT_4_IN6, I7 => NlwInverterSignal_EXP14_EXP_PT_4_IN7, I8 => NlwInverterSignal_EXP14_EXP_PT_4_IN8, I9 => NlwInverterSignal_EXP14_EXP_PT_4_IN9, I10 => NlwInverterSignal_EXP14_EXP_PT_4_IN10, I11 => NlwInverterSignal_EXP14_EXP_PT_4_IN11, I12 => NlwInverterSignal_EXP14_EXP_PT_4_IN12, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP14_EXP_PT_4 ); EXP14_EXP_PT_5_388 : X_AND16 port map ( I0 => NlwInverterSignal_EXP14_EXP_PT_5_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP14_EXP_PT_5_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP14_EXP_PT_5_IN4, I5 => NlwInverterSignal_EXP14_EXP_PT_5_IN5, I6 => NlwInverterSignal_EXP14_EXP_PT_5_IN6, I7 => NlwInverterSignal_EXP14_EXP_PT_5_IN7, I8 => NlwInverterSignal_EXP14_EXP_PT_5_IN8, I9 => NlwInverterSignal_EXP14_EXP_PT_5_IN9, I10 => NlwInverterSignal_EXP14_EXP_PT_5_IN10, I11 => NlwInverterSignal_EXP14_EXP_PT_5_IN11, I12 => n1param_0_IBUF, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP14_EXP_PT_5 ); EXP14_EXP_tsimrenamed_net_Q_389 : X_OR6 port map ( I0 => EXP14_EXP_PT_0, I1 => EXP14_EXP_PT_1, I2 => EXP14_EXP_PT_2, I3 => EXP14_EXP_PT_3, I4 => EXP14_EXP_PT_4, I5 => EXP14_EXP_PT_5, O => EXP14_EXP_tsimrenamed_net_Q ); EXP15_EXP_390 : X_BUF port map ( I => EXP15_EXP_tsimrenamed_net_Q, O => EXP15_EXP ); EXP15_EXP_PT_0_391 : X_AND16 port map ( I0 => NlwInverterSignal_EXP15_EXP_PT_0_IN0, I1 => state_FFT3, I2 => state_FFT2, I3 => NlwInverterSignal_EXP15_EXP_PT_0_IN3, I4 => NlwInverterSignal_EXP15_EXP_PT_0_IN4, I5 => NlwInverterSignal_EXP15_EXP_PT_0_IN5, I6 => NlwInverterSignal_EXP15_EXP_PT_0_IN6, I7 => NlwInverterSignal_EXP15_EXP_PT_0_IN7, I8 => NlwInverterSignal_EXP15_EXP_PT_0_IN8, I9 => NlwInverterSignal_EXP15_EXP_PT_0_IN9, I10 => NlwInverterSignal_EXP15_EXP_PT_0_IN10, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP15_EXP_PT_0 ); EXP15_EXP_PT_1_392 : X_AND16 port map ( I0 => NlwInverterSignal_EXP15_EXP_PT_1_IN0, I1 => state_FFT3, I2 => NlwInverterSignal_EXP15_EXP_PT_1_IN2, I3 => state_FFT1, I4 => NlwInverterSignal_EXP15_EXP_PT_1_IN4, I5 => NlwInverterSignal_EXP15_EXP_PT_1_IN5, I6 => NlwInverterSignal_EXP15_EXP_PT_1_IN6, I7 => NlwInverterSignal_EXP15_EXP_PT_1_IN7, I8 => NlwInverterSignal_EXP15_EXP_PT_1_IN8, I9 => NlwInverterSignal_EXP15_EXP_PT_1_IN9, I10 => NlwInverterSignal_EXP15_EXP_PT_1_IN10, I11 => Vcc, I12 => Vcc, I13 => Vcc, I14 => Vcc, I15 => Vcc, O => EXP15_EXP_PT_1 ); EXP15_EXP_tsimrenamed_net_Q_393 : X_OR2 port map ( I0 => EXP15_EXP_PT_0, I1 => EXP15_EXP_PT_1, O => EXP15_EXP_tsimrenamed_net_Q ); NlwInverterBlock_cnt_val_4_D2_PT_1_IN1 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_4_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_4_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_4_RSTF_IN0 ); NlwInverterBlock_cnt_val_4_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_4_RSTF_IN1 ); NlwInverterBlock_cnt_val_4_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_4_RSTF_IN2 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN2 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN4 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN4 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN5 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN6 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN7 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN8 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN9 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN10 ); NlwInverterBlock_cnt_val_4_EXP_PT_0_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_4_EXP_PT_0_IN11 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN0 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN3 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN5 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN6 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN7 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN8 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN9 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN10 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN11 ); NlwInverterBlock_cnt_val_4_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_4_EXP_PT_1_IN12 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN0 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN2 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN5 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN6 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN7 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN8 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN9 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN10 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN11 ); NlwInverterBlock_cnt_val_4_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_4_EXP_PT_2_IN12 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_0_D_IN0 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt_0_D1, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D_IN0 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_0_IN0 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN0 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_0_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN3 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN4 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN5 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN6 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN7 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN8 ); NlwInverterBlock_cnt_val_0_D2_PT_1_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_0_D2_PT_1_IN9 ); NlwInverterBlock_cnt_val_0_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_0_RSTF_IN0 ); NlwInverterBlock_cnt_val_0_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_0_RSTF_IN1 ); NlwInverterBlock_cnt_val_0_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_0_RSTF_IN2 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN1 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN2 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN3 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN4 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN5 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN6 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN7 ); NlwInverterBlock_cnt_val_0_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_cnt_val_0_EXP_PT_0_IN8 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN0 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN3 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN6 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN7 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN8 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN9 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN10 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN11 ); NlwInverterBlock_cnt_val_0_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_0_EXP_PT_1_IN12 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN0 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN2 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN6 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN7 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN8 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN9 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN10 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN11 ); NlwInverterBlock_cnt_val_0_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_0_EXP_PT_2_IN12 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN0 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN1 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN3 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN4 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN4 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN5 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN5 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN6 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN6 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN7 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN7 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN8 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN8 ); NlwInverterBlock_cnt_val_1_D2_PT_1_IN9 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_1_D2_PT_1_IN9 ); NlwInverterBlock_cnt_val_1_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_1_RSTF_IN0 ); NlwInverterBlock_cnt_val_1_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_1_RSTF_IN1 ); NlwInverterBlock_cnt_val_1_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_1_RSTF_IN2 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN0 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN3 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN6 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN7 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN8 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN9 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN10 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN11 ); NlwInverterBlock_cnt_val_1_EXP_PT_0_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_1_EXP_PT_0_IN12 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN2 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN5 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN6 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN7 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN8 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN9 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN10 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN11 ); NlwInverterBlock_cnt_val_1_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_1_EXP_PT_1_IN12 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN1 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN5 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN6 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN7 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN8 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN9 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN10 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN11 ); NlwInverterBlock_cnt_val_1_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_1_EXP_PT_2_IN12 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN0 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN0 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN1 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN2 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN3 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN4 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN5 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN6 ); NlwInverterBlock_cnt_val_2_D2_PT_2_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_2_D2_PT_2_IN7 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN0 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN0 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN1 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN2 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN3 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN4 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN5 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN6 ); NlwInverterBlock_cnt_val_2_D2_PT_3_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_2_D2_PT_3_IN7 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN0 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN1 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN1 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN2 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN2 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN3 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN4 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN5 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN6 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN7 ); NlwInverterBlock_cnt_val_2_D2_PT_4_IN8 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_2_D2_PT_4_IN8 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN0 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN1 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN1 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN2 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN2 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN3 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN4 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN5 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN6 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN7 ); NlwInverterBlock_cnt_val_2_D2_PT_5_IN8 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_2_D2_PT_5_IN8 ); NlwInverterBlock_cnt_val_2_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_2_RSTF_IN0 ); NlwInverterBlock_cnt_val_2_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_2_RSTF_IN1 ); NlwInverterBlock_cnt_val_2_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_2_RSTF_IN2 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN0 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN0 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN2 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN3 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN4 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN5 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN6 ); NlwInverterBlock_cnt_val_3_D2_PT_1_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_3_D2_PT_1_IN7 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN0 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN0 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN1 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN2 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN3 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN4 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN5 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN6 ); NlwInverterBlock_cnt_val_3_D2_PT_2_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_3_D2_PT_2_IN7 ); NlwInverterBlock_cnt_val_3_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_3_RSTF_IN0 ); NlwInverterBlock_cnt_val_3_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_3_RSTF_IN1 ); NlwInverterBlock_cnt_val_3_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_3_RSTF_IN2 ); NlwInverterBlock_cnt_val_3_EXP_PT_0_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_3_EXP_PT_0_IN0 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_1_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_10_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_10_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_10_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_10_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_10_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_10_RSTF_IN0 ); NlwInverterBlock_cnt_val_10_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_10_RSTF_IN1 ); NlwInverterBlock_cnt_val_10_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_10_RSTF_IN2 ); NlwInverterBlock_cnt_val_5_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_5_D2_PT_1_IN0 ); NlwInverterBlock_cnt_val_5_D2_PT_3_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_5_D2_PT_3_IN0 ); NlwInverterBlock_cnt_val_5_D2_PT_3_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_5_D2_PT_3_IN1 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN0 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN1 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN3 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN4 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN5 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN6 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN7 ); NlwInverterBlock_cnt_val_5_D2_PT_4_IN8 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_cnt_val_5_D2_PT_4_IN8 ); NlwInverterBlock_cnt_val_5_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_5_RSTF_IN0 ); NlwInverterBlock_cnt_val_5_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_5_RSTF_IN1 ); NlwInverterBlock_cnt_val_5_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_5_RSTF_IN2 ); NlwInverterBlock_cnt_val_6_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_6_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_6_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_6_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_6_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_6_RSTF_IN0 ); NlwInverterBlock_cnt_val_6_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_6_RSTF_IN1 ); NlwInverterBlock_cnt_val_6_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_6_RSTF_IN2 ); NlwInverterBlock_cnt_val_7_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_7_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_7_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_7_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_7_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_7_RSTF_IN0 ); NlwInverterBlock_cnt_val_7_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_7_RSTF_IN1 ); NlwInverterBlock_cnt_val_7_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_7_RSTF_IN2 ); NlwInverterBlock_cnt_val_8_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_8_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_8_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_8_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_8_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_8_RSTF_IN0 ); NlwInverterBlock_cnt_val_8_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_8_RSTF_IN1 ); NlwInverterBlock_cnt_val_8_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_8_RSTF_IN2 ); NlwInverterBlock_cnt_val_9_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_9_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_9_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_9_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_9_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_9_RSTF_IN0 ); NlwInverterBlock_cnt_val_9_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_9_RSTF_IN1 ); NlwInverterBlock_cnt_val_9_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_9_RSTF_IN2 ); NlwInverterBlock_Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_Inst_ren_wen_Inst_decim_cnt_2_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_11_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_11_D2_PT_0_IN2 ); NlwInverterBlock_cnt_val_11_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_11_D2_PT_1_IN1 ); NlwInverterBlock_cnt_val_11_RSTF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_val_11_RSTF_IN0 ); NlwInverterBlock_cnt_val_11_RSTF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_val_11_RSTF_IN1 ); NlwInverterBlock_cnt_val_11_RSTF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_val_11_RSTF_IN2 ); NlwInverterBlock_cnt_ovf1_D2_PT_2_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_ovf1_D2_PT_2_IN0 ); NlwInverterBlock_cnt_ovf1_D2_PT_4_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_ovf1_D2_PT_4_IN0 ); NlwInverterBlock_cnt_ovf1_D2_PT_4_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_ovf1_D2_PT_4_IN1 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN0 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN2 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN4 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN5 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN6 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN7 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN8 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN9 ); NlwInverterBlock_cnt_ovf1_D2_PT_5_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_ovf1_D2_PT_5_IN10 ); NlwInverterBlock_cnt_ovf1_SETF_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_ovf1_SETF_IN0 ); NlwInverterBlock_cnt_ovf1_SETF_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_ovf1_SETF_IN1 ); NlwInverterBlock_cnt_ovf1_SETF_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_ovf1_SETF_IN2 ); NlwInverterBlock_state_FFT2_D2_PT_0_IN1 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT2_D2_PT_0_IN1 ); NlwInverterBlock_state_FFT2_D2_PT_2_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_state_FFT2_D2_PT_2_IN1 ); NlwInverterBlock_state_FFT2_D2_PT_2_IN3 : X_INV port map ( I => cnt_ovf2, O => NlwInverterSignal_state_FFT2_D2_PT_2_IN3 ); NlwInverterBlock_state_FFT2_D2_PT_3_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT2_D2_PT_3_IN0 ); NlwInverterBlock_state_FFT2_D2_PT_3_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_state_FFT2_D2_PT_3_IN1 ); NlwInverterBlock_state_FFT2_D2_PT_3_IN3 : X_INV port map ( I => ren1_IBUF, O => NlwInverterSignal_state_FFT2_D2_PT_3_IN3 ); NlwInverterBlock_state_FFT2_D2_PT_4_IN0 : X_INV port map ( I => trig_mode_IBUF, O => NlwInverterSignal_state_FFT2_D2_PT_4_IN0 ); NlwInverterBlock_state_FFT2_D2_PT_4_IN1 : X_INV port map ( I => acqen_IBUF, O => NlwInverterSignal_state_FFT2_D2_PT_4_IN1 ); NlwInverterBlock_state_FFT2_D2_PT_4_IN2 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT2_D2_PT_4_IN2 ); NlwInverterBlock_state_FFT2_D2_PT_4_IN3 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_state_FFT2_D2_PT_4_IN3 ); NlwInverterBlock_state_FFT2_D2_PT_4_IN4 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_state_FFT2_D2_PT_4_IN4 ); NlwInverterBlock_state_FFT1_D2_PT_0_IN1 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT1_D2_PT_0_IN1 ); NlwInverterBlock_state_FFT1_D2_PT_1_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_state_FFT1_D2_PT_1_IN2 ); NlwInverterBlock_state_FFT1_D2_PT_1_IN3 : X_INV port map ( I => cnt_ovf1, O => NlwInverterSignal_state_FFT1_D2_PT_1_IN3 ); NlwInverterBlock_state_FFT1_D2_PT_2_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_state_FFT1_D2_PT_2_IN1 ); NlwInverterBlock_state_FFT1_D2_PT_2_IN3 : X_INV port map ( I => cnt_ovf2, O => NlwInverterSignal_state_FFT1_D2_PT_2_IN3 ); NlwInverterBlock_state_FFT1_D2_PT_3_IN1 : X_INV port map ( I => acqen_IBUF, O => NlwInverterSignal_state_FFT1_D2_PT_3_IN1 ); NlwInverterBlock_state_FFT1_D2_PT_3_IN2 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT1_D2_PT_3_IN2 ); NlwInverterBlock_state_FFT1_D2_PT_3_IN3 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_state_FFT1_D2_PT_3_IN3 ); NlwInverterBlock_state_FFT1_D2_PT_3_IN4 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_state_FFT1_D2_PT_3_IN4 ); NlwInverterBlock_state_FFT3_D2_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_state_FFT3_D2_IN0 ); NlwInverterBlock_state_FFT3_D2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_state_FFT3_D2_IN2 ); NlwInverterBlock_state_FFT3_D2_IN3 : X_INV port map ( I => ren1_IBUF, O => NlwInverterSignal_state_FFT3_D2_IN3 ); NlwInverterBlock_cnt_ovf2_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_cnt_ovf2_D2_PT_1_IN0 ); NlwInverterBlock_cnt_ovf2_D2_PT_3_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_ovf2_D2_PT_3_IN0 ); NlwInverterBlock_cnt_ovf2_D2_PT_3_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_ovf2_D2_PT_3_IN1 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN2 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN3 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN4 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN5 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN6 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN7 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN8 ); NlwInverterBlock_cnt_ovf2_D2_PT_4_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_ovf2_D2_PT_4_IN9 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN1 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN3 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN4 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN5 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN6 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN7 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN8 ); NlwInverterBlock_cnt_ovf2_D2_PT_5_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_cnt_ovf2_D2_PT_5_IN9 ); NlwInverterBlock_decim_flag_OBUF_D2_PT_0_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_decim_flag_OBUF_D2_PT_0_IN1 ); NlwInverterBlock_decim_flag_OBUF_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_decim_flag_OBUF_D2_PT_1_IN0 ); NlwInverterBlock_fsmst_0_tsimcreated_set_and_noreset_IN0 : X_INV port map ( I => fsmst_0_RSTF, O => NlwInverterSignal_fsmst_0_tsimcreated_set_and_noreset_IN0 ); NlwInverterBlock_fsmst_0_RSTF_IN0 : X_INV port map ( I => fsmst_0_fsmst_0_RSTF_INT_UIM, O => NlwInverterSignal_fsmst_0_RSTF_IN0 ); NlwInverterBlock_fsmst_0_RSTF_IN1 : X_INV port map ( I => fsmst_0_fsmst_0_RSTF_INT_UIM, O => NlwInverterSignal_fsmst_0_RSTF_IN1 ); NlwInverterBlock_fsmst_1_tsimcreated_set_and_noreset_IN0 : X_INV port map ( I => fsmst_1_RSTF, O => NlwInverterSignal_fsmst_1_tsimcreated_set_and_noreset_IN0 ); NlwInverterBlock_fsmst_2_tsimcreated_set_and_noreset_IN0 : X_INV port map ( I => fsmst_2_RSTF, O => NlwInverterSignal_fsmst_2_tsimcreated_set_and_noreset_IN0 ); NlwInverterBlock_counten_OBUF_D_IN0 : X_INV port map ( I => counten_OBUF_D1, O => NlwInverterSignal_counten_OBUF_D_IN0 ); NlwInverterBlock_counten_OBUF_D2_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_counten_OBUF_D2_PT_0_IN2 ); NlwInverterBlock_counten_OBUF_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_counten_OBUF_D2_PT_1_IN1 ); NlwInverterBlock_ren2_OBUF_D_IN0 : X_INV port map ( I => ren2_OBUF_D1, O => NlwInverterSignal_ren2_OBUF_D_IN0 ); NlwInverterBlock_ren2_OBUF_D2_PT_0_IN4 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN4 ); NlwInverterBlock_ren2_OBUF_D2_PT_0_IN5 : X_INV port map ( I => decim_ratio_1_IBUF, O => NlwInverterSignal_ren2_OBUF_D2_PT_0_IN5 ); NlwInverterBlock_ren2_OBUF_D2_PT_1_IN4 : X_INV port map ( I => decim_ratio_0_IBUF, O => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN4 ); NlwInverterBlock_ren2_OBUF_D2_PT_1_IN5 : X_INV port map ( I => decim_ratio_1_IBUF, O => NlwInverterSignal_ren2_OBUF_D2_PT_1_IN5 ); NlwInverterBlock_ren2_OBUF_D2_PT_2_IN4 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN4 ); NlwInverterBlock_ren2_OBUF_D2_PT_2_IN5 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(1), O => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN5 ); NlwInverterBlock_ren2_OBUF_D2_PT_2_IN6 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(2), O => NlwInverterSignal_ren2_OBUF_D2_PT_2_IN6 ); NlwInverterBlock_ren2_OBUF_D2_PT_3_IN4 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN4 ); NlwInverterBlock_ren2_OBUF_D2_PT_3_IN5 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(1), O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN5 ); NlwInverterBlock_ren2_OBUF_D2_PT_3_IN6 : X_INV port map ( I => decim_ratio_0_IBUF, O => NlwInverterSignal_ren2_OBUF_D2_PT_3_IN6 ); NlwInverterBlock_rst2_OBUF_D_IN0 : X_INV port map ( I => rst2_OBUF_D1, O => NlwInverterSignal_rst2_OBUF_D_IN0 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN0 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN3 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN4 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN5 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN6 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN7 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN8 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN9 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN10 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN11 ); NlwInverterBlock_rst2_OBUF_EXP_PT_0_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_rst2_OBUF_EXP_PT_0_IN12 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN0 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN3 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN4 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN5 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN6 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN7 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN8 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN9 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN10 ); NlwInverterBlock_rst2_OBUF_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_rst2_OBUF_EXP_PT_1_IN11 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN2 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN3 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN3 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN4 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN5 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN6 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN7 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN8 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN9 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN10 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN11 ); NlwInverterBlock_rst2_OBUF_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_rst2_OBUF_EXP_PT_2_IN12 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN1 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN3 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN3 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN4 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN5 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN6 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN7 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN8 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN9 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN10 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN11 ); NlwInverterBlock_rst2_OBUF_EXP_PT_3_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_rst2_OBUF_EXP_PT_3_IN12 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN1 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN3 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN3 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN4 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN5 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN6 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN7 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN8 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN9 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN10 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN11 ); NlwInverterBlock_rst2_OBUF_EXP_PT_4_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_rst2_OBUF_EXP_PT_4_IN12 ); NlwInverterBlock_trigger_en_OBUF_D_IN0 : X_INV port map ( I => trigger_en_OBUF_D1, O => NlwInverterSignal_trigger_en_OBUF_D_IN0 ); NlwInverterBlock_wen2_OBUF_D_IN0 : X_INV port map ( I => wen2_OBUF_D1, O => NlwInverterSignal_wen2_OBUF_D_IN0 ); NlwInverterBlock_wen2_OBUF_D2_PT_0_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_wen2_OBUF_D2_PT_0_IN1 ); NlwInverterBlock_wen2_OBUF_D2_PT_1_IN3 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN3 ); NlwInverterBlock_wen2_OBUF_D2_PT_1_IN4 : X_INV port map ( I => decim_ratio_1_IBUF, O => NlwInverterSignal_wen2_OBUF_D2_PT_1_IN4 ); NlwInverterBlock_wen2_OBUF_D2_PT_2_IN3 : X_INV port map ( I => decim_ratio_0_IBUF, O => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN3 ); NlwInverterBlock_wen2_OBUF_D2_PT_2_IN4 : X_INV port map ( I => decim_ratio_1_IBUF, O => NlwInverterSignal_wen2_OBUF_D2_PT_2_IN4 ); NlwInverterBlock_wen2_OBUF_D2_PT_3_IN3 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN3 ); NlwInverterBlock_wen2_OBUF_D2_PT_3_IN4 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(1), O => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN4 ); NlwInverterBlock_wen2_OBUF_D2_PT_3_IN5 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(2), O => NlwInverterSignal_wen2_OBUF_D2_PT_3_IN5 ); NlwInverterBlock_wen2_OBUF_D2_PT_4_IN3 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(0), O => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN3 ); NlwInverterBlock_wen2_OBUF_D2_PT_4_IN4 : X_INV port map ( I => Inst_ren_wen_Inst_decim_cnt(1), O => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN4 ); NlwInverterBlock_wen2_OBUF_D2_PT_4_IN5 : X_INV port map ( I => decim_ratio_0_IBUF, O => NlwInverterSignal_wen2_OBUF_D2_PT_4_IN5 ); NlwInverterBlock_fsmst_0_fsmst_0_SETF_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN0 ); NlwInverterBlock_fsmst_0_fsmst_0_SETF_D2_PT_1_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_fsmst_0_fsmst_0_SETF_D2_PT_1_IN2 ); NlwInverterBlock_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN1 ); NlwInverterBlock_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_1_IN2 ); NlwInverterBlock_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN0 ); NlwInverterBlock_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_fsmst_0_fsmst_0_RSTF_INT_D2_PT_2_IN2 ); NlwInverterBlock_fsmst_1_fsmst_1_SETF_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_1_fsmst_1_SETF_D2_PT_1_IN0 ); NlwInverterBlock_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN0 ); NlwInverterBlock_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_0_IN1 ); NlwInverterBlock_fsmst_1_fsmst_1_RSTF_D2_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_fsmst_1_fsmst_1_RSTF_D2_PT_1_IN1 ); NlwInverterBlock_fsmst_2_fsmst_2_SETF_D2_PT_0_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_0_IN0 ); NlwInverterBlock_fsmst_2_fsmst_2_SETF_D2_PT_1_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_fsmst_2_fsmst_2_SETF_D2_PT_1_IN0 ); NlwInverterBlock_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN0 ); NlwInverterBlock_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_fsmst_2_fsmst_2_RSTF_D2_PT_1_IN1 ); NlwInverterBlock_EXP6_EXP_tsimrenamed_net_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN0 ); NlwInverterBlock_EXP6_EXP_tsimrenamed_net_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN1 ); NlwInverterBlock_EXP6_EXP_tsimrenamed_net_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP6_EXP_tsimrenamed_net_IN2 ); NlwInverterBlock_EXP7_EXP_PT_0_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP7_EXP_PT_0_IN3 ); NlwInverterBlock_EXP7_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP7_EXP_PT_0_IN6 ); NlwInverterBlock_EXP7_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP7_EXP_PT_0_IN7 ); NlwInverterBlock_EXP7_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP7_EXP_PT_0_IN8 ); NlwInverterBlock_EXP7_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP7_EXP_PT_0_IN9 ); NlwInverterBlock_EXP7_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP7_EXP_PT_0_IN10 ); NlwInverterBlock_EXP7_EXP_PT_0_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP7_EXP_PT_0_IN11 ); NlwInverterBlock_EXP7_EXP_PT_0_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP7_EXP_PT_0_IN12 ); NlwInverterBlock_EXP7_EXP_PT_1_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP7_EXP_PT_1_IN2 ); NlwInverterBlock_EXP7_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP7_EXP_PT_1_IN6 ); NlwInverterBlock_EXP7_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP7_EXP_PT_1_IN7 ); NlwInverterBlock_EXP7_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP7_EXP_PT_1_IN8 ); NlwInverterBlock_EXP7_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP7_EXP_PT_1_IN9 ); NlwInverterBlock_EXP7_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP7_EXP_PT_1_IN10 ); NlwInverterBlock_EXP7_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP7_EXP_PT_1_IN11 ); NlwInverterBlock_EXP7_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP7_EXP_PT_1_IN12 ); NlwInverterBlock_EXP8_EXP_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP8_EXP_PT_0_IN2 ); NlwInverterBlock_EXP8_EXP_PT_1_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP8_EXP_PT_1_IN1 ); NlwInverterBlock_EXP8_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP8_EXP_PT_2_IN2 ); NlwInverterBlock_EXP8_EXP_PT_2_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP8_EXP_PT_2_IN3 ); NlwInverterBlock_EXP8_EXP_PT_2_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP8_EXP_PT_2_IN4 ); NlwInverterBlock_EXP8_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP8_EXP_PT_2_IN5 ); NlwInverterBlock_EXP8_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP8_EXP_PT_2_IN6 ); NlwInverterBlock_EXP8_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP8_EXP_PT_2_IN7 ); NlwInverterBlock_EXP8_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP8_EXP_PT_2_IN8 ); NlwInverterBlock_EXP8_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP8_EXP_PT_2_IN9 ); NlwInverterBlock_EXP8_EXP_PT_3_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP8_EXP_PT_3_IN0 ); NlwInverterBlock_EXP8_EXP_PT_3_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP8_EXP_PT_3_IN3 ); NlwInverterBlock_EXP8_EXP_PT_3_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP8_EXP_PT_3_IN4 ); NlwInverterBlock_EXP8_EXP_PT_3_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP8_EXP_PT_3_IN5 ); NlwInverterBlock_EXP8_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP8_EXP_PT_3_IN6 ); NlwInverterBlock_EXP8_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP8_EXP_PT_3_IN7 ); NlwInverterBlock_EXP8_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP8_EXP_PT_3_IN8 ); NlwInverterBlock_EXP8_EXP_PT_3_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP8_EXP_PT_3_IN9 ); NlwInverterBlock_EXP8_EXP_PT_3_IN10 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP8_EXP_PT_3_IN10 ); NlwInverterBlock_EXP8_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP8_EXP_PT_4_IN0 ); NlwInverterBlock_EXP8_EXP_PT_4_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP8_EXP_PT_4_IN2 ); NlwInverterBlock_EXP8_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP8_EXP_PT_4_IN4 ); NlwInverterBlock_EXP8_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP8_EXP_PT_4_IN5 ); NlwInverterBlock_EXP8_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP8_EXP_PT_4_IN6 ); NlwInverterBlock_EXP8_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP8_EXP_PT_4_IN7 ); NlwInverterBlock_EXP8_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP8_EXP_PT_4_IN8 ); NlwInverterBlock_EXP8_EXP_PT_4_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP8_EXP_PT_4_IN9 ); NlwInverterBlock_EXP8_EXP_PT_4_IN10 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP8_EXP_PT_4_IN10 ); NlwInverterBlock_EXP9_EXP_PT_2_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP9_EXP_PT_2_IN1 ); NlwInverterBlock_EXP9_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP9_EXP_PT_2_IN2 ); NlwInverterBlock_EXP9_EXP_PT_3_IN1 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_EXP9_EXP_PT_3_IN1 ); NlwInverterBlock_EXP9_EXP_PT_3_IN2 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP9_EXP_PT_3_IN2 ); NlwInverterBlock_EXP9_EXP_PT_3_IN3 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP9_EXP_PT_3_IN3 ); NlwInverterBlock_EXP9_EXP_PT_3_IN4 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP9_EXP_PT_3_IN4 ); NlwInverterBlock_EXP9_EXP_PT_3_IN5 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP9_EXP_PT_3_IN5 ); NlwInverterBlock_EXP9_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP9_EXP_PT_3_IN6 ); NlwInverterBlock_EXP9_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP9_EXP_PT_3_IN7 ); NlwInverterBlock_EXP9_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP9_EXP_PT_3_IN8 ); NlwInverterBlock_EXP9_EXP_PT_4_IN1 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP9_EXP_PT_4_IN1 ); NlwInverterBlock_EXP9_EXP_PT_4_IN2 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP9_EXP_PT_4_IN2 ); NlwInverterBlock_EXP9_EXP_PT_4_IN3 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP9_EXP_PT_4_IN3 ); NlwInverterBlock_EXP9_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP9_EXP_PT_4_IN4 ); NlwInverterBlock_EXP9_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP9_EXP_PT_4_IN5 ); NlwInverterBlock_EXP9_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP9_EXP_PT_4_IN6 ); NlwInverterBlock_EXP9_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP9_EXP_PT_4_IN7 ); NlwInverterBlock_EXP9_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP9_EXP_PT_4_IN8 ); NlwInverterBlock_EXP9_EXP_PT_5_IN1 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP9_EXP_PT_5_IN1 ); NlwInverterBlock_EXP9_EXP_PT_5_IN2 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP9_EXP_PT_5_IN2 ); NlwInverterBlock_EXP9_EXP_PT_5_IN3 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP9_EXP_PT_5_IN3 ); NlwInverterBlock_EXP9_EXP_PT_5_IN4 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP9_EXP_PT_5_IN4 ); NlwInverterBlock_EXP9_EXP_PT_5_IN5 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP9_EXP_PT_5_IN5 ); NlwInverterBlock_EXP9_EXP_PT_5_IN6 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP9_EXP_PT_5_IN6 ); NlwInverterBlock_EXP9_EXP_PT_5_IN7 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP9_EXP_PT_5_IN7 ); NlwInverterBlock_EXP9_EXP_PT_5_IN8 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP9_EXP_PT_5_IN8 ); NlwInverterBlock_EXP10_EXP_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_EXP10_EXP_PT_1_IN0 ); NlwInverterBlock_EXP10_EXP_PT_3_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP10_EXP_PT_3_IN0 ); NlwInverterBlock_EXP10_EXP_PT_3_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP10_EXP_PT_3_IN1 ); NlwInverterBlock_EXP10_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_EXP10_EXP_PT_4_IN0 ); NlwInverterBlock_EXP10_EXP_PT_4_IN2 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP10_EXP_PT_4_IN2 ); NlwInverterBlock_EXP10_EXP_PT_4_IN3 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP10_EXP_PT_4_IN3 ); NlwInverterBlock_EXP10_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP10_EXP_PT_4_IN4 ); NlwInverterBlock_EXP10_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP10_EXP_PT_4_IN5 ); NlwInverterBlock_EXP10_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP10_EXP_PT_4_IN6 ); NlwInverterBlock_EXP10_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP10_EXP_PT_4_IN7 ); NlwInverterBlock_EXP10_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP10_EXP_PT_4_IN8 ); NlwInverterBlock_EXP10_EXP_PT_5_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP10_EXP_PT_5_IN1 ); NlwInverterBlock_EXP10_EXP_PT_5_IN4 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP10_EXP_PT_5_IN4 ); NlwInverterBlock_EXP10_EXP_PT_5_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP10_EXP_PT_5_IN5 ); NlwInverterBlock_EXP10_EXP_PT_5_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP10_EXP_PT_5_IN6 ); NlwInverterBlock_EXP10_EXP_PT_5_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP10_EXP_PT_5_IN7 ); NlwInverterBlock_EXP10_EXP_PT_5_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP10_EXP_PT_5_IN8 ); NlwInverterBlock_EXP10_EXP_PT_5_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP10_EXP_PT_5_IN9 ); NlwInverterBlock_EXP10_EXP_PT_5_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP10_EXP_PT_5_IN10 ); NlwInverterBlock_EXP10_EXP_PT_5_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP10_EXP_PT_5_IN11 ); NlwInverterBlock_EXP11_EXP_PT_1_IN0 : X_INV port map ( I => state_FFT3, O => NlwInverterSignal_EXP11_EXP_PT_1_IN0 ); NlwInverterBlock_EXP11_EXP_PT_3_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP11_EXP_PT_3_IN0 ); NlwInverterBlock_EXP11_EXP_PT_3_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP11_EXP_PT_3_IN1 ); NlwInverterBlock_EXP11_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP11_EXP_PT_4_IN0 ); NlwInverterBlock_EXP11_EXP_PT_4_IN1 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP11_EXP_PT_4_IN1 ); NlwInverterBlock_EXP11_EXP_PT_4_IN2 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP11_EXP_PT_4_IN2 ); NlwInverterBlock_EXP11_EXP_PT_4_IN3 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP11_EXP_PT_4_IN3 ); NlwInverterBlock_EXP11_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP11_EXP_PT_4_IN4 ); NlwInverterBlock_EXP11_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP11_EXP_PT_4_IN5 ); NlwInverterBlock_EXP11_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP11_EXP_PT_4_IN6 ); NlwInverterBlock_EXP11_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP11_EXP_PT_4_IN8 ); NlwInverterBlock_EXP11_EXP_PT_5_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP11_EXP_PT_5_IN0 ); NlwInverterBlock_EXP11_EXP_PT_5_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP11_EXP_PT_5_IN2 ); NlwInverterBlock_EXP11_EXP_PT_5_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP11_EXP_PT_5_IN6 ); NlwInverterBlock_EXP11_EXP_PT_5_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP11_EXP_PT_5_IN7 ); NlwInverterBlock_EXP11_EXP_PT_5_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP11_EXP_PT_5_IN8 ); NlwInverterBlock_EXP11_EXP_PT_5_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP11_EXP_PT_5_IN9 ); NlwInverterBlock_EXP11_EXP_PT_5_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP11_EXP_PT_5_IN10 ); NlwInverterBlock_EXP11_EXP_PT_5_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP11_EXP_PT_5_IN11 ); NlwInverterBlock_EXP11_EXP_PT_5_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP11_EXP_PT_5_IN12 ); NlwInverterBlock_EXP12_EXP_PT_0_IN0 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP12_EXP_PT_0_IN0 ); NlwInverterBlock_EXP12_EXP_PT_0_IN1 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP12_EXP_PT_0_IN1 ); NlwInverterBlock_EXP12_EXP_PT_1_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP12_EXP_PT_1_IN2 ); NlwInverterBlock_EXP12_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP12_EXP_PT_1_IN5 ); NlwInverterBlock_EXP12_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP12_EXP_PT_1_IN6 ); NlwInverterBlock_EXP12_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP12_EXP_PT_1_IN7 ); NlwInverterBlock_EXP12_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP12_EXP_PT_1_IN8 ); NlwInverterBlock_EXP12_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP12_EXP_PT_1_IN9 ); NlwInverterBlock_EXP12_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP12_EXP_PT_1_IN10 ); NlwInverterBlock_EXP12_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP12_EXP_PT_1_IN11 ); NlwInverterBlock_EXP12_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP12_EXP_PT_1_IN12 ); NlwInverterBlock_EXP12_EXP_PT_2_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP12_EXP_PT_2_IN1 ); NlwInverterBlock_EXP12_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP12_EXP_PT_2_IN5 ); NlwInverterBlock_EXP12_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP12_EXP_PT_2_IN6 ); NlwInverterBlock_EXP12_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP12_EXP_PT_2_IN7 ); NlwInverterBlock_EXP12_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP12_EXP_PT_2_IN8 ); NlwInverterBlock_EXP12_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP12_EXP_PT_2_IN9 ); NlwInverterBlock_EXP12_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP12_EXP_PT_2_IN10 ); NlwInverterBlock_EXP12_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP12_EXP_PT_2_IN11 ); NlwInverterBlock_EXP12_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP12_EXP_PT_2_IN12 ); NlwInverterBlock_EXP12_EXP_PT_3_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP12_EXP_PT_3_IN0 ); NlwInverterBlock_EXP12_EXP_PT_3_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP12_EXP_PT_3_IN3 ); NlwInverterBlock_EXP12_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP12_EXP_PT_3_IN6 ); NlwInverterBlock_EXP12_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP12_EXP_PT_3_IN7 ); NlwInverterBlock_EXP12_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP12_EXP_PT_3_IN8 ); NlwInverterBlock_EXP12_EXP_PT_3_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP12_EXP_PT_3_IN9 ); NlwInverterBlock_EXP12_EXP_PT_3_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP12_EXP_PT_3_IN10 ); NlwInverterBlock_EXP12_EXP_PT_3_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP12_EXP_PT_3_IN11 ); NlwInverterBlock_EXP12_EXP_PT_3_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP12_EXP_PT_3_IN12 ); NlwInverterBlock_EXP12_EXP_PT_3_IN13 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP12_EXP_PT_3_IN13 ); NlwInverterBlock_EXP12_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP12_EXP_PT_4_IN0 ); NlwInverterBlock_EXP12_EXP_PT_4_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP12_EXP_PT_4_IN2 ); NlwInverterBlock_EXP12_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP12_EXP_PT_4_IN6 ); NlwInverterBlock_EXP12_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP12_EXP_PT_4_IN7 ); NlwInverterBlock_EXP12_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP12_EXP_PT_4_IN8 ); NlwInverterBlock_EXP12_EXP_PT_4_IN9 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP12_EXP_PT_4_IN9 ); NlwInverterBlock_EXP12_EXP_PT_4_IN10 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP12_EXP_PT_4_IN10 ); NlwInverterBlock_EXP12_EXP_PT_4_IN11 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP12_EXP_PT_4_IN11 ); NlwInverterBlock_EXP12_EXP_PT_4_IN12 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP12_EXP_PT_4_IN12 ); NlwInverterBlock_EXP12_EXP_PT_4_IN13 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP12_EXP_PT_4_IN13 ); NlwInverterBlock_EXP13_EXP_PT_0_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP13_EXP_PT_0_IN2 ); NlwInverterBlock_EXP13_EXP_PT_0_IN3 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP13_EXP_PT_0_IN3 ); NlwInverterBlock_EXP13_EXP_PT_0_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP13_EXP_PT_0_IN4 ); NlwInverterBlock_EXP13_EXP_PT_0_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP13_EXP_PT_0_IN5 ); NlwInverterBlock_EXP13_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP13_EXP_PT_0_IN6 ); NlwInverterBlock_EXP13_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP13_EXP_PT_0_IN7 ); NlwInverterBlock_EXP13_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP13_EXP_PT_0_IN8 ); NlwInverterBlock_EXP13_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP13_EXP_PT_0_IN9 ); NlwInverterBlock_EXP13_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP13_EXP_PT_0_IN10 ); NlwInverterBlock_EXP13_EXP_PT_0_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP13_EXP_PT_0_IN11 ); NlwInverterBlock_EXP13_EXP_PT_0_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP13_EXP_PT_0_IN12 ); NlwInverterBlock_EXP13_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP13_EXP_PT_1_IN0 ); NlwInverterBlock_EXP13_EXP_PT_1_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP13_EXP_PT_1_IN3 ); NlwInverterBlock_EXP13_EXP_PT_1_IN4 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_EXP13_EXP_PT_1_IN4 ); NlwInverterBlock_EXP13_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP13_EXP_PT_1_IN5 ); NlwInverterBlock_EXP13_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP13_EXP_PT_1_IN6 ); NlwInverterBlock_EXP13_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP13_EXP_PT_1_IN7 ); NlwInverterBlock_EXP13_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP13_EXP_PT_1_IN8 ); NlwInverterBlock_EXP13_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP13_EXP_PT_1_IN9 ); NlwInverterBlock_EXP13_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP13_EXP_PT_1_IN10 ); NlwInverterBlock_EXP13_EXP_PT_1_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP13_EXP_PT_1_IN11 ); NlwInverterBlock_EXP13_EXP_PT_1_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP13_EXP_PT_1_IN12 ); NlwInverterBlock_EXP13_EXP_PT_1_IN13 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP13_EXP_PT_1_IN13 ); NlwInverterBlock_EXP13_EXP_PT_2_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP13_EXP_PT_2_IN0 ); NlwInverterBlock_EXP13_EXP_PT_2_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP13_EXP_PT_2_IN3 ); NlwInverterBlock_EXP13_EXP_PT_2_IN4 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP13_EXP_PT_2_IN4 ); NlwInverterBlock_EXP13_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP13_EXP_PT_2_IN5 ); NlwInverterBlock_EXP13_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP13_EXP_PT_2_IN6 ); NlwInverterBlock_EXP13_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP13_EXP_PT_2_IN7 ); NlwInverterBlock_EXP13_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP13_EXP_PT_2_IN8 ); NlwInverterBlock_EXP13_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP13_EXP_PT_2_IN9 ); NlwInverterBlock_EXP13_EXP_PT_2_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP13_EXP_PT_2_IN10 ); NlwInverterBlock_EXP13_EXP_PT_2_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP13_EXP_PT_2_IN11 ); NlwInverterBlock_EXP13_EXP_PT_2_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP13_EXP_PT_2_IN12 ); NlwInverterBlock_EXP13_EXP_PT_3_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP13_EXP_PT_3_IN0 ); NlwInverterBlock_EXP13_EXP_PT_3_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP13_EXP_PT_3_IN2 ); NlwInverterBlock_EXP13_EXP_PT_3_IN4 : X_INV port map ( I => cnt_val(0), O => NlwInverterSignal_EXP13_EXP_PT_3_IN4 ); NlwInverterBlock_EXP13_EXP_PT_3_IN5 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP13_EXP_PT_3_IN5 ); NlwInverterBlock_EXP13_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP13_EXP_PT_3_IN6 ); NlwInverterBlock_EXP13_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP13_EXP_PT_3_IN7 ); NlwInverterBlock_EXP13_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP13_EXP_PT_3_IN8 ); NlwInverterBlock_EXP13_EXP_PT_3_IN9 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP13_EXP_PT_3_IN9 ); NlwInverterBlock_EXP13_EXP_PT_3_IN10 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP13_EXP_PT_3_IN10 ); NlwInverterBlock_EXP13_EXP_PT_3_IN11 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP13_EXP_PT_3_IN11 ); NlwInverterBlock_EXP13_EXP_PT_3_IN12 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP13_EXP_PT_3_IN12 ); NlwInverterBlock_EXP13_EXP_PT_3_IN13 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP13_EXP_PT_3_IN13 ); NlwInverterBlock_EXP13_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP13_EXP_PT_4_IN0 ); NlwInverterBlock_EXP13_EXP_PT_4_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP13_EXP_PT_4_IN2 ); NlwInverterBlock_EXP13_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(1), O => NlwInverterSignal_EXP13_EXP_PT_4_IN4 ); NlwInverterBlock_EXP13_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP13_EXP_PT_4_IN5 ); NlwInverterBlock_EXP13_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP13_EXP_PT_4_IN6 ); NlwInverterBlock_EXP13_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP13_EXP_PT_4_IN7 ); NlwInverterBlock_EXP13_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP13_EXP_PT_4_IN8 ); NlwInverterBlock_EXP13_EXP_PT_4_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP13_EXP_PT_4_IN9 ); NlwInverterBlock_EXP13_EXP_PT_4_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP13_EXP_PT_4_IN10 ); NlwInverterBlock_EXP13_EXP_PT_4_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP13_EXP_PT_4_IN11 ); NlwInverterBlock_EXP13_EXP_PT_4_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP13_EXP_PT_4_IN12 ); NlwInverterBlock_EXP14_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP14_EXP_PT_1_IN0 ); NlwInverterBlock_EXP14_EXP_PT_1_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP14_EXP_PT_1_IN3 ); NlwInverterBlock_EXP14_EXP_PT_1_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP14_EXP_PT_1_IN4 ); NlwInverterBlock_EXP14_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP14_EXP_PT_1_IN5 ); NlwInverterBlock_EXP14_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP14_EXP_PT_1_IN6 ); NlwInverterBlock_EXP14_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP14_EXP_PT_1_IN7 ); NlwInverterBlock_EXP14_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP14_EXP_PT_1_IN8 ); NlwInverterBlock_EXP14_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP14_EXP_PT_1_IN9 ); NlwInverterBlock_EXP14_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP14_EXP_PT_1_IN10 ); NlwInverterBlock_EXP14_EXP_PT_2_IN2 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP14_EXP_PT_2_IN2 ); NlwInverterBlock_EXP14_EXP_PT_2_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP14_EXP_PT_2_IN3 ); NlwInverterBlock_EXP14_EXP_PT_2_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP14_EXP_PT_2_IN4 ); NlwInverterBlock_EXP14_EXP_PT_2_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP14_EXP_PT_2_IN5 ); NlwInverterBlock_EXP14_EXP_PT_2_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP14_EXP_PT_2_IN6 ); NlwInverterBlock_EXP14_EXP_PT_2_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP14_EXP_PT_2_IN7 ); NlwInverterBlock_EXP14_EXP_PT_2_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP14_EXP_PT_2_IN8 ); NlwInverterBlock_EXP14_EXP_PT_2_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP14_EXP_PT_2_IN9 ); NlwInverterBlock_EXP14_EXP_PT_3_IN1 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP14_EXP_PT_3_IN1 ); NlwInverterBlock_EXP14_EXP_PT_3_IN3 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP14_EXP_PT_3_IN3 ); NlwInverterBlock_EXP14_EXP_PT_3_IN4 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP14_EXP_PT_3_IN4 ); NlwInverterBlock_EXP14_EXP_PT_3_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP14_EXP_PT_3_IN5 ); NlwInverterBlock_EXP14_EXP_PT_3_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP14_EXP_PT_3_IN6 ); NlwInverterBlock_EXP14_EXP_PT_3_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP14_EXP_PT_3_IN7 ); NlwInverterBlock_EXP14_EXP_PT_3_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP14_EXP_PT_3_IN8 ); NlwInverterBlock_EXP14_EXP_PT_3_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP14_EXP_PT_3_IN9 ); NlwInverterBlock_EXP14_EXP_PT_4_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP14_EXP_PT_4_IN0 ); NlwInverterBlock_EXP14_EXP_PT_4_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP14_EXP_PT_4_IN2 ); NlwInverterBlock_EXP14_EXP_PT_4_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP14_EXP_PT_4_IN4 ); NlwInverterBlock_EXP14_EXP_PT_4_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP14_EXP_PT_4_IN5 ); NlwInverterBlock_EXP14_EXP_PT_4_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP14_EXP_PT_4_IN6 ); NlwInverterBlock_EXP14_EXP_PT_4_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP14_EXP_PT_4_IN7 ); NlwInverterBlock_EXP14_EXP_PT_4_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP14_EXP_PT_4_IN8 ); NlwInverterBlock_EXP14_EXP_PT_4_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP14_EXP_PT_4_IN9 ); NlwInverterBlock_EXP14_EXP_PT_4_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP14_EXP_PT_4_IN10 ); NlwInverterBlock_EXP14_EXP_PT_4_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP14_EXP_PT_4_IN11 ); NlwInverterBlock_EXP14_EXP_PT_4_IN12 : X_INV port map ( I => cnt_val(2), O => NlwInverterSignal_EXP14_EXP_PT_4_IN12 ); NlwInverterBlock_EXP14_EXP_PT_5_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP14_EXP_PT_5_IN0 ); NlwInverterBlock_EXP14_EXP_PT_5_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP14_EXP_PT_5_IN2 ); NlwInverterBlock_EXP14_EXP_PT_5_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP14_EXP_PT_5_IN4 ); NlwInverterBlock_EXP14_EXP_PT_5_IN5 : X_INV port map ( I => cnt_val(5), O => NlwInverterSignal_EXP14_EXP_PT_5_IN5 ); NlwInverterBlock_EXP14_EXP_PT_5_IN6 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP14_EXP_PT_5_IN6 ); NlwInverterBlock_EXP14_EXP_PT_5_IN7 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP14_EXP_PT_5_IN7 ); NlwInverterBlock_EXP14_EXP_PT_5_IN8 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP14_EXP_PT_5_IN8 ); NlwInverterBlock_EXP14_EXP_PT_5_IN9 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP14_EXP_PT_5_IN9 ); NlwInverterBlock_EXP14_EXP_PT_5_IN10 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP14_EXP_PT_5_IN10 ); NlwInverterBlock_EXP14_EXP_PT_5_IN11 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP14_EXP_PT_5_IN11 ); NlwInverterBlock_EXP15_EXP_PT_0_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP15_EXP_PT_0_IN0 ); NlwInverterBlock_EXP15_EXP_PT_0_IN3 : X_INV port map ( I => state_FFT1, O => NlwInverterSignal_EXP15_EXP_PT_0_IN3 ); NlwInverterBlock_EXP15_EXP_PT_0_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP15_EXP_PT_0_IN4 ); NlwInverterBlock_EXP15_EXP_PT_0_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP15_EXP_PT_0_IN5 ); NlwInverterBlock_EXP15_EXP_PT_0_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP15_EXP_PT_0_IN6 ); NlwInverterBlock_EXP15_EXP_PT_0_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP15_EXP_PT_0_IN7 ); NlwInverterBlock_EXP15_EXP_PT_0_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP15_EXP_PT_0_IN8 ); NlwInverterBlock_EXP15_EXP_PT_0_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP15_EXP_PT_0_IN9 ); NlwInverterBlock_EXP15_EXP_PT_0_IN10 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP15_EXP_PT_0_IN10 ); NlwInverterBlock_EXP15_EXP_PT_1_IN0 : X_INV port map ( I => cnt_val(4), O => NlwInverterSignal_EXP15_EXP_PT_1_IN0 ); NlwInverterBlock_EXP15_EXP_PT_1_IN2 : X_INV port map ( I => state_FFT2, O => NlwInverterSignal_EXP15_EXP_PT_1_IN2 ); NlwInverterBlock_EXP15_EXP_PT_1_IN4 : X_INV port map ( I => cnt_val(10), O => NlwInverterSignal_EXP15_EXP_PT_1_IN4 ); NlwInverterBlock_EXP15_EXP_PT_1_IN5 : X_INV port map ( I => cnt_val(6), O => NlwInverterSignal_EXP15_EXP_PT_1_IN5 ); NlwInverterBlock_EXP15_EXP_PT_1_IN6 : X_INV port map ( I => cnt_val(7), O => NlwInverterSignal_EXP15_EXP_PT_1_IN6 ); NlwInverterBlock_EXP15_EXP_PT_1_IN7 : X_INV port map ( I => cnt_val(8), O => NlwInverterSignal_EXP15_EXP_PT_1_IN7 ); NlwInverterBlock_EXP15_EXP_PT_1_IN8 : X_INV port map ( I => cnt_val(9), O => NlwInverterSignal_EXP15_EXP_PT_1_IN8 ); NlwInverterBlock_EXP15_EXP_PT_1_IN9 : X_INV port map ( I => cnt_val(11), O => NlwInverterSignal_EXP15_EXP_PT_1_IN9 ); NlwInverterBlock_EXP15_EXP_PT_1_IN10 : X_INV port map ( I => cnt_val(3), O => NlwInverterSignal_EXP15_EXP_PT_1_IN10 ); NlwBlockROC : X_ROC generic map (ROC_WIDTH => 100 ns) port map (O => PRLD); end Structure;