Release 6.1i - xst G.23 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.20 s | Elapsed : 0.00 / 1.00 s --> Reading design: fifo2.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : fifo2.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : fifo2 Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : fifo2 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : fifo2.lso verilog2001 : YES Clock Enable : YES wysiwyg : NO ========================================================================= WARNING:Xst:1885 - LSO file is empty, default list of libraries is used ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd in Library work. Architecture behavioral of Entity decim is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd in Library work. Architecture behavioral of Entity ren_wen is up to date. Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd in Library work. Architecture behavioral of Entity fifo2 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Set property "ENUM_ENCODING = 000 001 010 011 100 101 110" for signal . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/decim.vhd. Found 3-bit comparator less for signal <$n0006> created at line 62. Found 3-bit adder for signal <$n0015> created at line 63. Found 3-bit register for signal . Summary: inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/ren_wen.vhd. Unit synthesized. Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo2.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 7 | | Transitions | 21 | | Inputs | 7 | | Outputs | 9 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 13-bit adder for signal <$n0028> created at line 435. Found 12-bit comparator less for signal <$n0029> created at line 404. Found 13-bit comparator less for signal <$n0030> created at line 435. Found 12-bit comparator greatequal for signal <$n0035> created at line 404. Found 13-bit comparator greatequal for signal <$n0036> created at line 435. Found 1-bit register for signal . Found 1-bit register for signal . Found 12-bit up counter for signal . Found 12-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 4 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 3 3-bit register : 1 1-bit register : 2 # Counters : 2 12-bit up counter : 2 # Adders/Subtractors : 2 3-bit adder : 1 13-bit adder : 1 # Comparators : 5 3-bit comparator less : 1 12-bit comparator less : 1 13-bit comparator less : 1 12-bit comparator greatequal : 1 13-bit comparator greatequal : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = T ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_val1_7 implementation constraint: INIT=s : cnt_val1_8 implementation constraint: INIT=s : cnt_val1_5 implementation constraint: INIT=s : cnt_val2_8 implementation constraint: INIT=s : cnt_val1_6 implementation constraint: INIT=s : cnt_val1_4 implementation constraint: INIT=s : cnt_val1_3 implementation constraint: INIT=s : cnt_val2_9 implementation constraint: INIT=s : cnt_val2_11 implementation constraint: INIT=s : cnt_val2_10 implementation constraint: INIT=s : cnt_val2_0 implementation constraint: INIT=s : cnt_val2_1 implementation constraint: INIT=s : cnt_val2_2 implementation constraint: INIT=s : cnt_val2_3 implementation constraint: INIT=s : cnt_val2_4 implementation constraint: INIT=s : cnt_val2_5 implementation constraint: INIT=s : cnt_val2_6 implementation constraint: INIT=s : cnt_val2_7 implementation constraint: INIT=s : cnt_val1_9 implementation constraint: INIT=s : cnt_val1_11 implementation constraint: INIT=s : cnt_val1_10 implementation constraint: INIT=s : cnt_val1_0 implementation constraint: INIT=s : cnt_val1_1 implementation constraint: INIT=s : cnt_val1_2 Optimizing unit ... implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 Optimizing unit ... ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : fifo2.ngr Top Level Output File Name : fifo2 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : xc9500xl Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 18 Macro Statistics : # Registers : 11 # 1-bit register : 11 # Comparators : 5 # 12-bit comparator greatequal: 1 # 12-bit comparator less : 1 # 13-bit comparator greatequal: 1 # 13-bit comparator less : 1 # 3-bit comparator less : 1 # Xors : 8 # 1-bit xor2 : 8 Cell Usage : # BELS : 366 # AND2 : 117 # AND3 : 15 # AND4 : 3 # AND5 : 1 # GND : 1 # INV : 158 # OR2 : 35 # OR3 : 4 # OR4 : 1 # OR5 : 1 # XOR2 : 30 # FlipFlops/Latches : 32 # FDCE : 27 # FDPE : 2 # FTC : 3 # IO Buffers : 18 # IBUF : 12 # OBUF : 6 ========================================================================= CPU : 1.70 / 2.00 s | Elapsed : 1.00 / 2.00 s --> Total memory usage is 49736 kilobytes