cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: fifo2 Date: 2-18-2004, 12:12PM Device Used: XC9572XL-5-VQ44 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 35 /72 ( 49%) 152 /360 ( 42%) 23 /72 ( 32%) 19 /34 ( 56%) 63 /216 ( 29%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 8 8 | I/O : 15 13 Output : 9 9 | GCK/IO : 2 1 Bidirectional : 0 0 | GTS/IO : 1 1 GCK : 1 1 | GSR/IO : 1 0 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 19 19 MACROCELL RESOURCES: Total Macrocells Available 72 Registered Macrocells 23 Non-registered Macrocell driving I/O 6 GLOBAL RESOURCES: Signal 'acqclk' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'reset' mapped onto global set/reset net GSR. POWER DATA: There are 35 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 35 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State Inst_ren_wen/Inst_decim/cnt<0> 2 3 FB3_14 STD 13 I/O (b) SET Inst_ren_wen/Inst_decim/cnt<1> 2 4 FB3_13 STD (b) (b) SET Inst_ren_wen/Inst_decim/cnt<2> 2 5 FB3_12 STD (b) (b) SET cnt_ovf1 20 18 FB1_1 STD (b) (b) RESET cnt_ovf2 7 13 FB2_18 STD (b) (b) RESET cnt_val<0> 7 13 FB1_8 STD 42 I/O I SET cnt_val<10> 3 4 FB4_18 STD (b) (b) SET cnt_val<11> 3 4 FB4_17 STD 28 I/O I SET cnt_val<1> 10 14 FB1_12 STD (b) (b) SET cnt_val<2> 12 15 FB1_15 STD 2 I/O (b) SET cnt_val<3> 11 15 FB1_14 STD 1 GCK/I/O I SET cnt_val<4> 10 15 FB1_10 STD (b) (b) SET cnt_val<5> 7 15 FB1_6 STD 41 I/O (b) SET cnt_val<6> 3 4 FB4_16 STD (b) (b) SET cnt_val<7> 3 4 FB4_15 STD 27 I/O (b) SET cnt_val<8> 3 4 FB4_13 STD (b) (b) SET cnt_val<9> 3 4 FB4_12 STD (b) (b) SET counten 2 3 FB3_15 STD FAST 14 I/O O decim_flag 2 3 FB2_2 STD FAST 29 I/O O fsmst<0> 2 2 FB3_2 STD FAST 5 I/O O RESET fsmst<1> 2 2 FB3_8 STD FAST 7 I/O O RESET fsmst<2> 2 2 FB3_11 STD FAST 12 I/O O RESET fsmst_0/fsmst_0_RSTF__$INT 3 3 FB3_16 STD 18 I/O (b) fsmst_0/fsmst_0_SETF 2 3 FB3_10 STD (b) (b) fsmst_1/fsmst_1_RSTF 2 3 FB3_9 STD 8 I/O (b) fsmst_1/fsmst_1_SETF 2 3 FB3_7 STD (b) (b) fsmst_2/fsmst_2_RSTF 2 3 FB3_6 STD (b) (b) fsmst_2/fsmst_2_SETF 2 3 FB3_5 STD 6 I/O (b) ren2 4 9 FB4_14 STD FAST 23 I/O O rst2 1 3 FB1_2 STD FAST 39 I/O O state_FFT1 4 7 FB3_17 STD 16 I/O I RESET state_FFT2 5 8 FB3_18 STD (b) (b) RESET state_FFT3 1 4 FB3_4 STD (b) (b) RESET trigger_en 1 3 FB2_8 STD FAST 32 I/O O wen2 5 9 FB4_5 STD FAST 20 I/O O ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use acqclk FB1_9 43 GCK/I/O GCK acqen FB4_17 28 I/O I decim_ratio<0> FB2_6 31 I/O I decim_ratio<1> FB2_11 34 GTS/I/O I n1param<0> FB4_8 21 I/O I n1param<1> FB1_5 40 I/O I ren1 FB1_8 42 I/O I reset FB2_9 33 GSR/I/O GSR/I trig_mode FB3_17 16 I/O I trigger FB1_14 1 GCK/I/O I End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 8 18 18 78 1/0 9 FB2 3 13 13 10 2/0 9 FB3 16 17 17 37 4/0 9 FB4 8 15 15 27 2/0 7 ---- ----- ----- ----- 35 152 9/0 34 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use cnt_ovf1 20 15<- 0 0 FB1_1 STD (b) (b) rst2 1 1<- /\5 0 FB1_2 STD 39 I/O O (unused) 0 0 /\1 4 FB1_3 (b) (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 \/2 3 FB1_5 40 I/O I cnt_val<5> 7 2<- 0 0 FB1_6 STD 41 I/O (b) (unused) 0 0 \/5 0 FB1_7 (b) (b) cnt_val<0> 7 5<- \/3 0 FB1_8 STD 42 I/O I (unused) 0 0 \/5 0 FB1_9 43 GCK/I/O GCK cnt_val<4> 10 8<- \/3 0 FB1_10 STD (b) (b) (unused) 0 0 \/5 0 FB1_11 44 GCK/I/O (b) cnt_val<1> 10 8<- \/3 0 FB1_12 STD (b) (b) (unused) 0 0 \/5 0 FB1_13 (b) (b) cnt_val<3> 11 8<- \/2 0 FB1_14 STD 1 GCK/I/O I cnt_val<2> 12 7<- 0 0 FB1_15 STD 2 I/O (b) (unused) 0 0 /\5 0 FB1_16 (b) (b) (unused) 0 0 \/5 0 FB1_17 3 I/O (b) (unused) 0 0 \/5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: cnt_ovf1 7: cnt_val<3> 13: cnt_val<9> 2: cnt_val<0> 8: cnt_val<4> 14: n1param<0> 3: cnt_val<10> 9: cnt_val<5> 15: n1param<1> 4: cnt_val<11> 10: cnt_val<6> 16: state_FFT1 5: cnt_val<1> 11: cnt_val<7> 17: state_FFT2 6: cnt_val<2> 12: cnt_val<8> 18: state_FFT3 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs cnt_ovf1 XXXXXXXXXXXXXXXXXX...................... 18 18 rst2 ...............XXX...................... 3 3 cnt_val<5> .XXXXXXXXXXXX..XXX...................... 15 15 cnt_val<0> .XXX..XXXXXXX..XXX...................... 13 13 cnt_val<4> .XXXXXXXXXXXX..XXX...................... 15 15 cnt_val<1> .XXXX.XXXXXXX..XXX...................... 14 14 cnt_val<3> .XXXXXXXXXXXX..XXX...................... 15 15 cnt_val<2> .XXXXXXXXXXXX..XXX...................... 15 15 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 (b) decim_flag 2 0 0 3 FB2_2 STD 29 I/O O (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 30 I/O (unused) 0 0 0 5 FB2_6 31 I/O I (unused) 0 0 0 5 FB2_7 (b) trigger_en 1 0 0 4 FB2_8 STD 32 I/O O (unused) 0 0 0 5 FB2_9 33 GSR/I/O GSR/I (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 34 GTS/I/O I (unused) 0 0 0 5 FB2_12 (b) (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 36 GTS/I/O (unused) 0 0 0 5 FB2_15 37 I/O (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 \/2 3 FB2_17 38 I/O (b) cnt_ovf2 7 2<- 0 0 FB2_18 STD (b) (b) Signals Used by Logic in Function Block 1: cnt_ovf2 6: cnt_val<5> 10: cnt_val<9> 2: cnt_val<10> 7: cnt_val<6> 11: state_FFT1 3: cnt_val<11> 8: cnt_val<7> 12: state_FFT2 4: cnt_val<3> 9: cnt_val<8> 13: state_FFT3 5: cnt_val<4> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs decim_flag ..........XXX........................... 3 3 trigger_en ..........XXX........................... 3 3 cnt_ovf2 XXXXXXXXXXXXX........................... 13 13 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 17/37 Number of signals used by logic mapping into function block: 17 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB3_1 (b) fsmst<0> 2 0 0 3 FB3_2 STD 5 I/O O (unused) 0 0 0 5 FB3_3 (b) state_FFT3 1 0 0 4 FB3_4 STD (b) (b) fsmst_2/fsmst_2_SETF 2 0 0 3 FB3_5 STD 6 I/O (b) fsmst_2/fsmst_2_RSTF 2 0 0 3 FB3_6 STD (b) (b) fsmst_1/fsmst_1_SETF 2 0 0 3 FB3_7 STD (b) (b) fsmst<1> 2 0 0 3 FB3_8 STD 7 I/O O fsmst_1/fsmst_1_RSTF 2 0 0 3 FB3_9 STD 8 I/O (b) fsmst_0/fsmst_0_SETF 2 0 0 3 FB3_10 STD (b) (b) fsmst<2> 2 0 0 3 FB3_11 STD 12 I/O O Inst_ren_wen/Inst_decim/cnt<2> 2 0 0 3 FB3_12 STD (b) (b) Inst_ren_wen/Inst_decim/cnt<1> 2 0 0 3 FB3_13 STD (b) (b) Inst_ren_wen/Inst_decim/cnt<0> 2 0 0 3 FB3_14 STD 13 I/O (b) counten 2 0 0 3 FB3_15 STD 14 I/O O fsmst_0/fsmst_0_RSTF__$INT 3 0 0 2 FB3_16 STD 18 I/O (b) state_FFT1 4 0 0 1 FB3_17 STD 16 I/O I state_FFT2 5 0 0 0 FB3_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_ren_wen/Inst_decim/cnt<0> 7: fsmst_0/fsmst_0_SETF 13: state_FFT1 2: Inst_ren_wen/Inst_decim/cnt<1> 8: fsmst_1/fsmst_1_RSTF 14: state_FFT2 3: acqen 9: fsmst_1/fsmst_1_SETF 15: state_FFT3 4: cnt_ovf1 10: fsmst_2/fsmst_2_RSTF 16: trig_mode 5: cnt_ovf2 11: fsmst_2/fsmst_2_SETF 17: trigger 6: fsmst_0/fsmst_0_RSTF__$INT 12: ren1 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs fsmst<0> .....XX................................. 2 2 state_FFT3 ...........XXXX......................... 4 4 fsmst_2/fsmst_2_SETF ............XXX......................... 3 3 fsmst_2/fsmst_2_RSTF ............XXX......................... 3 3 fsmst_1/fsmst_1_SETF ............XXX......................... 3 3 fsmst<1> .......XX............................... 2 2 fsmst_1/fsmst_1_RSTF ............XXX......................... 3 3 fsmst_0/fsmst_0_SETF ............XXX......................... 3 3 fsmst<2> .........XX............................. 2 2 Inst_ren_wen/Inst_decim/cnt<2> XX..........XXX......................... 5 5 Inst_ren_wen/Inst_decim/cnt<1> X...........XXX......................... 4 4 Inst_ren_wen/Inst_decim/cnt<0> ............XXX......................... 3 3 counten ............XXX......................... 3 3 fsmst_0/fsmst_0_RSTF__$INT ............XXX......................... 3 3 state_FFT1 ..XXX.......XXXX........................ 7 7 state_FFT2 ..X.X......XXXXXX....................... 8 8 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 19 I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) wen2 5 0 0 0 FB4_5 STD 20 I/O O (unused) 0 0 0 5 FB4_6 (b) (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 21 I/O I (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 22 I/O cnt_val<9> 3 0 0 2 FB4_12 STD (b) (b) cnt_val<8> 3 0 0 2 FB4_13 STD (b) (b) ren2 4 0 0 1 FB4_14 STD 23 I/O O cnt_val<7> 3 0 0 2 FB4_15 STD 27 I/O (b) cnt_val<6> 3 0 0 2 FB4_16 STD (b) (b) cnt_val<11> 3 0 0 2 FB4_17 STD 28 I/O I cnt_val<10> 3 0 0 2 FB4_18 STD (b) (b) Signals Used by Logic in Function Block 1: Inst_ren_wen/Inst_decim/cnt<0> 6: cnt_val<6> 11: decim_ratio<1> 2: Inst_ren_wen/Inst_decim/cnt<1> 7: cnt_val<7> 12: reset 3: Inst_ren_wen/Inst_decim/cnt<2> 8: cnt_val<8> 13: state_FFT1 4: cnt_val<10> 9: cnt_val<9> 14: state_FFT2 5: cnt_val<11> 10: decim_ratio<0> 15: state_FFT3 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs wen2 XXX......XXXXXX......................... 9 9 cnt_val<9> ........X...XXX......................... 4 4 cnt_val<8> .......X....XXX......................... 4 4 ren2 XXX......XXXXXX......................... 9 9 cnt_val<7> ......X.....XXX......................... 4 4 cnt_val<6> .....X......XXX......................... 4 4 cnt_val<11> ....X.......XXX......................... 4 4 cnt_val<10> ...X........XXX......................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. !Inst_ren_wen/Inst_decim/cnt<0>.T = !state_FFT2 & !state_FFT1 # state_FFT1 & !state_FFT3; Inst_ren_wen/Inst_decim/cnt<0>.CLK = acqclk; // GCK !Inst_ren_wen/Inst_decim/cnt<0>.AR = reset; // GSR Inst_ren_wen/Inst_decim/cnt<1>.T = Inst_ren_wen/Inst_decim/cnt<0> & state_FFT2 & !state_FFT1 # Inst_ren_wen/Inst_decim/cnt<0> & state_FFT1 & state_FFT3; Inst_ren_wen/Inst_decim/cnt<1>.CLK = acqclk; // GCK !Inst_ren_wen/Inst_decim/cnt<1>.AR = reset; // GSR Inst_ren_wen/Inst_decim/cnt<2>.T = Inst_ren_wen/Inst_decim/cnt<0> & Inst_ren_wen/Inst_decim/cnt<1> & state_FFT2 & !state_FFT1 # Inst_ren_wen/Inst_decim/cnt<0> & Inst_ren_wen/Inst_decim/cnt<1> & state_FFT1 & state_FFT3; Inst_ren_wen/Inst_decim/cnt<2>.CLK = acqclk; // GCK !Inst_ren_wen/Inst_decim/cnt<2>.AR = reset; // GSR cnt_ovf1.D = cnt_ovf1 & !state_FFT3 # cnt_ovf1 & state_FFT2 & state_FFT1 # cnt_ovf1 & !state_FFT2 & !state_FFT1 # !cnt_val<4> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<1> ;Imported pterms FB1_2 # !cnt_val<4> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<0> # !cnt_val<0> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<1> # !cnt_val<0> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<1> # !cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<1> ;Imported pterms FB1_18 # !cnt_val<4> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<1> # !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<1> & n1param<0> # !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<1> & n1param<0> # !cnt_val<4> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<0> ;Imported pterms FB1_17 # !cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<1> # !cnt_val<4> & !cnt_val<0> & !cnt_val<1> & !cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<0> # !cnt_val<4> & !cnt_val<0> & !cnt_val<1> & !cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<0> # !cnt_val<4> & !cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 & n1param<1> & n1param<0> # !cnt_val<4> & !cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 & n1param<1> & n1param<0>; cnt_ovf1.CLK = acqclk; // GCK cnt_ovf1.AP = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_ovf2.D = !state_FFT3 & cnt_ovf2 # state_FFT2 & state_FFT1 & cnt_ovf2 # !state_FFT2 & !state_FFT1 & cnt_ovf2 # !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 ;Imported pterms FB2_17 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_ovf2.CLK = acqclk; // GCK cnt_val<0>.T = !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 ;Imported pterms FB1_7 # cnt_val<0> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<0> & !state_FFT2 & state_FFT1 & state_FFT3 # !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<0>.CLK = acqclk; // GCK cnt_val<0>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<10>.T = cnt_val<10> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<10> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<10>.CLK = acqclk; // GCK cnt_val<10>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<11>.T = cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<11>.CLK = acqclk; // GCK cnt_val<11>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<1>.D = !cnt_val<4> & !cnt_val<0> & cnt_val<1> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> ;Imported pterms FB1_11 # cnt_val<1> & !state_FFT3 # cnt_val<1> & state_FFT2 & state_FFT1 # cnt_val<1> & !state_FFT2 & !state_FFT1 # !cnt_val<0> & cnt_val<1> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # cnt_val<0> & !cnt_val<1> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 ;Imported pterms FB1_10 # cnt_val<0> & !cnt_val<1> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & cnt_val<0> & !cnt_val<1> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & cnt_val<0> & !cnt_val<1> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<1>.CLK = acqclk; // GCK cnt_val<1>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<2>.D = !cnt_val<0> & cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<1> & cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<4> & !cnt_val<0> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<4> & !cnt_val<1> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> ;Imported pterms FB1_14 # cnt_val<2> & !state_FFT3 # cnt_val<2> & state_FFT2 & state_FFT1 ;Imported pterms FB1_16 # cnt_val<2> & !state_FFT2 & !state_FFT1 # cnt_val<0> & cnt_val<1> & !cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<0> & cnt_val<1> & !cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 # !cnt_val<4> & cnt_val<0> & cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & cnt_val<0> & cnt_val<1> & !cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<2>.CLK = acqclk; // GCK cnt_val<2>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<3>.D = !cnt_val<0> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<1> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> ;Imported pterms FB1_13 # cnt_val<3> & !state_FFT3 # cnt_val<3> & state_FFT2 & state_FFT1 # cnt_val<3> & !state_FFT2 & !state_FFT1 # !cnt_val<2> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3 ;Imported pterms FB1_12 # !cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<0> & cnt_val<1> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<0> & cnt_val<1> & cnt_val<2> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<3>.CLK = acqclk; // GCK cnt_val<3>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<4>.D = cnt_val<4> & !state_FFT3 ;Imported pterms FB1_9 # cnt_val<4> & state_FFT2 & state_FFT1 # cnt_val<4> & !state_FFT2 & !state_FFT1 # cnt_val<4> & !cnt_val<0> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # cnt_val<4> & !cnt_val<1> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # cnt_val<4> & !cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> ;Imported pterms FB1_8 # cnt_val<4> & !cnt_val<2> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> # !cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # !cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<4>.CLK = acqclk; // GCK cnt_val<4>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<5>.D = cnt_val<5> & !state_FFT3 # cnt_val<5> & state_FFT2 & state_FFT1 # cnt_val<5> & !state_FFT2 & !state_FFT1 # !cnt_val<4> & !cnt_val<3> & !cnt_val<10> & cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> ;Imported pterms FB1_5 # cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<4> & cnt_val<0> & cnt_val<1> & cnt_val<2> & cnt_val<3> & !cnt_val<10> & !cnt_val<5> & !cnt_val<6> & !cnt_val<7> & !cnt_val<8> & !cnt_val<9> & !cnt_val<11> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<5>.CLK = acqclk; // GCK cnt_val<5>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<6>.T = cnt_val<6> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<6> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<6>.CLK = acqclk; // GCK cnt_val<6>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<7>.T = cnt_val<7> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<7> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<7>.CLK = acqclk; // GCK cnt_val<7>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<8>.T = cnt_val<8> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<8> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<8>.CLK = acqclk; // GCK cnt_val<8>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; cnt_val<9>.T = cnt_val<9> & state_FFT2 & !state_FFT1 & state_FFT3 # cnt_val<9> & !state_FFT2 & state_FFT1 & state_FFT3; cnt_val<9>.CLK = acqclk; // GCK cnt_val<9>.AR = !state_FFT2 & !state_FFT1 & !state_FFT3; !counten = state_FFT2 & !state_FFT1 & state_FFT3 # !state_FFT2 & state_FFT1 & state_FFT3; decim_flag = !state_FFT2 & state_FFT3 # state_FFT1 & !state_FFT3; fsmst<0>.D = Gnd; fsmst<0>.CLK = Gnd; fsmst<0>.AP = fsmst_0/fsmst_0_SETF; fsmst<0>.AR = !fsmst_0/fsmst_0_RSTF__$INT; fsmst_0/fsmst_0_RSTF__$INT = state_FFT2 & state_FFT1 & state_FFT3 # state_FFT2 & !state_FFT1 & !state_FFT3 # !state_FFT2 & !state_FFT1 & state_FFT3; fsmst_0/fsmst_0_SETF = state_FFT2 & state_FFT1 & state_FFT3 # state_FFT2 & !state_FFT1 & !state_FFT3; fsmst<1>.D = Gnd; fsmst<1>.CLK = Gnd; fsmst<1>.AP = fsmst_1/fsmst_1_SETF; fsmst<1>.AR = fsmst_1/fsmst_1_RSTF; fsmst_1/fsmst_1_RSTF = !state_FFT1 & !state_FFT3 # !state_FFT2 & state_FFT1 & state_FFT3; fsmst_1/fsmst_1_SETF = state_FFT2 & state_FFT3 # state_FFT1 & !state_FFT3; fsmst<2>.D = Gnd; fsmst<2>.CLK = Gnd; fsmst<2>.AP = fsmst_2/fsmst_2_SETF; fsmst<2>.AR = fsmst_2/fsmst_2_RSTF; fsmst_2/fsmst_2_RSTF = state_FFT2 & state_FFT3 # !state_FFT1 & !state_FFT3; fsmst_2/fsmst_2_SETF = !state_FFT2 & state_FFT1 # state_FFT1 & !state_FFT3; !ren2 = reset & !Inst_ren_wen/Inst_decim/cnt<0> & state_FFT2 & state_FFT1 & state_FFT3 & !decim_ratio<1> # reset & state_FFT2 & state_FFT1 & state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # reset & !Inst_ren_wen/Inst_decim/cnt<0> & !Inst_ren_wen/Inst_decim/cnt<1> & !Inst_ren_wen/Inst_decim/cnt<2> & state_FFT2 & state_FFT1 & state_FFT3 # reset & !Inst_ren_wen/Inst_decim/cnt<0> & !Inst_ren_wen/Inst_decim/cnt<1> & state_FFT2 & state_FFT1 & state_FFT3 & !decim_ratio<0>; !rst2 = ;Imported pterms FB1_3 !state_FFT2 & !state_FFT1 & !state_FFT3; state_FFT1.T = acqen & state_FFT2 & state_FFT1 & !state_FFT3 # !cnt_ovf1 & state_FFT2 & !state_FFT1 & state_FFT3 # !state_FFT2 & state_FFT1 & state_FFT3 & !cnt_ovf2 # trig_mode & !acqen & !state_FFT2 & !state_FFT1 & !state_FFT3; state_FFT1.CLK = acqclk; // GCK !state_FFT1.AR = reset; // GSR state_FFT2.T = acqen & state_FFT2 & state_FFT1 & !state_FFT3 # !ren1 & !state_FFT2 & state_FFT1 & !state_FFT3 # state_FFT2 & state_FFT1 & state_FFT3 & trigger # !state_FFT2 & state_FFT1 & state_FFT3 & !cnt_ovf2 # !trig_mode & !acqen & !state_FFT2 & !state_FFT1 & !state_FFT3; state_FFT2.CLK = acqclk; // GCK !state_FFT2.AR = reset; // GSR state_FFT3.T = !ren1 & state_FFT2 & !state_FFT1 & !state_FFT3; state_FFT3.CLK = acqclk; // GCK !state_FFT3.AR = reset; // GSR !trigger_en = state_FFT2 & state_FFT1 & state_FFT3; !wen2 = reset & !state_FFT2 & state_FFT1 & state_FFT3 # reset & !Inst_ren_wen/Inst_decim/cnt<0> & state_FFT2 & state_FFT3 & !decim_ratio<1> # reset & state_FFT2 & state_FFT3 & !decim_ratio<0> & !decim_ratio<1> # reset & !Inst_ren_wen/Inst_decim/cnt<0> & !Inst_ren_wen/Inst_decim/cnt<1> & !Inst_ren_wen/Inst_decim/cnt<2> & state_FFT2 & state_FFT3 # reset & !Inst_ren_wen/Inst_decim/cnt<0> & !Inst_ren_wen/Inst_decim/cnt<1> & state_FFT2 & state_FFT3 & !decim_ratio<0>; Legend: .COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC9572XL-5-VQ44 ----------------------------------- /44 43 42 41 40 39 38 37 36 35 34 33 \ | 1 32 | | 2 31 | | 3 30 | | 4 29 | | 5 XC9572XL-5-VQ44 28 | | 6 27 | | 7 26 | | 8 25 | | 9 24 | | 10 23 | | 11 22 | \ 12 13 14 15 16 17 18 19 20 21 22 23 / ----------------------------------- Pin Signal Pin Signal No. Name No. Name 1 trigger 23 ren2 2 TIE 24 TDO 3 TIE 25 GND 4 GND 26 VCC 5 fsmst<0> 27 TIE 6 TIE 28 acqen 7 fsmst<1> 29 decim_flag 8 TIE 30 TIE 9 TDI 31 decim_ratio<0> 10 TMS 32 trigger_en 11 TCK 33 reset 12 fsmst<2> 34 decim_ratio<1> 13 TIE 35 VCC 14 counten 36 TIE 15 VCC 37 TIE 16 trig_mode 38 TIE 17 GND 39 rst2 18 TIE 40 n1param<1> 19 TIE 41 TIE 20 wen2 42 ren1 21 n1param<0> 43 acqclk 22 TIE 44 TIE Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9572xl-5-VQ44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25