Release 6.1.03i - netgen G.26
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
Reading design fifo2.nga ...
  Flattening design ...
  Flattening design completed.
  Specializing design ...
  Specializing design completed.
  Preping physical only global signals ...
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist fifo2_timesim.vhd ...
Writing VHDL SDF file fifo2_timesim.sdf ...
Total memory usage is 32632 kilobytes