-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Tue Dec 07 09:43:16 2004 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Waveform -- 2) To use this as a user modifiable testbench do the following: -- - Save it as a file with a .vhd extension (i.e. File->Save As...) -- - Add it to your project as a testbench source (i.e. Project->Add Source...) -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY fifo1_tbw IS END fifo1_tbw; ARCHITECTURE testbench_arch OF fifo1_tbw IS -- If you get a compiler error on the following line, -- from the menu do Options->Configuration select VHDL 87 FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt"; COMPONENT fifo1 PORT ( reset : In std_logic; clk : In std_logic; acqen : In std_logic; rst1 : Out std_logic; wen1 : Out std_logic; ren1 : Out std_logic ); END COMPONENT; SIGNAL reset : std_logic; SIGNAL clk : std_logic; SIGNAL acqen : std_logic; SIGNAL rst1 : std_logic; SIGNAL wen1 : std_logic; SIGNAL ren1 : std_logic; BEGIN UUT : fifo1 PORT MAP ( reset => reset, clk => clk, acqen => acqen, rst1 => rst1, wen1 => wen1, ren1 => ren1 ); PROCESS -- clock process for clk, BEGIN CLOCK_LOOP : LOOP clk <= transport '0'; WAIT FOR 6 ns; clk <= transport '1'; WAIT FOR 6 ns; WAIT FOR 44 ns; clk <= transport '0'; WAIT FOR 44 ns; END LOOP CLOCK_LOOP; END PROCESS; PROCESS -- Process for clk VARIABLE TX_OUT : LINE; VARIABLE TX_ERROR : INTEGER := 0; PROCEDURE CHECK_rst1( next_rst1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN -- If compiler error ("/=" is ambiguous) occurs in the next line of code -- change compiler settings to use explicit declarations only IF (rst1 /= next_rst1) THEN STD.TEXTIO.write(TX_LOC,string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'("ns rst1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_rst1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_wen1( next_wen1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN -- If compiler error ("/=" is ambiguous) occurs in the next line of code -- change compiler settings to use explicit declarations only IF (wen1 /= next_wen1) THEN STD.TEXTIO.write(TX_LOC,string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'("ns wen1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_wen1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_ren1( next_ren1 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN -- If compiler error ("/=" is ambiguous) occurs in the next line of code -- change compiler settings to use explicit declarations only IF (ren1 /= next_ren1) THEN STD.TEXTIO.write(TX_LOC,string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'("ns ren1=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren1); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_ren1); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; BEGIN -- -------------------- reset <= transport '0'; acqen <= transport '1'; -- -------------------- WAIT FOR 12 ns; -- Time=12 ns CHECK_rst1('0',12); CHECK_wen1('1',12); CHECK_ren1('1',12); -- -------------------- WAIT FOR 100 ns; -- Time=112 ns CHECK_rst1('0',112); CHECK_wen1('1',112); CHECK_ren1('1',112); -- -------------------- WAIT FOR 88 ns; -- Time=200 ns reset <= transport '1'; -- -------------------- WAIT FOR 12 ns; -- Time=212 ns CHECK_rst1('0',212); CHECK_wen1('1',212); CHECK_ren1('1',212); -- -------------------- WAIT FOR 100 ns; -- Time=312 ns CHECK_rst1('0',312); CHECK_wen1('1',312); CHECK_ren1('1',312); -- -------------------- WAIT FOR 88 ns; -- Time=400 ns acqen <= transport '0'; -- -------------------- WAIT FOR 12 ns; -- Time=412 ns CHECK_rst1('1',412); CHECK_wen1('0',412); CHECK_ren1('1',412); -- -------------------- WAIT FOR 100 ns; -- Time=512 ns CHECK_rst1('1',512); CHECK_wen1('0',512); CHECK_ren1('1',512); -- -------------------- WAIT FOR 100 ns; -- Time=612 ns CHECK_rst1('1',612); CHECK_wen1('0',612); CHECK_ren1('1',612); -- -------------------- WAIT FOR 100 ns; -- Time=712 ns CHECK_rst1('1',712); CHECK_wen1('0',712); CHECK_ren1('1',712); -- -------------------- WAIT FOR 100 ns; -- Time=812 ns CHECK_rst1('1',812); CHECK_wen1('0',812); CHECK_ren1('1',812); -- -------------------- WAIT FOR 100 ns; -- Time=912 ns CHECK_rst1('1',912); CHECK_wen1('0',912); CHECK_ren1('1',912); -- -------------------- WAIT FOR 100 ns; -- Time=1012 ns CHECK_rst1('1',1012); CHECK_wen1('0',1012); CHECK_ren1('1',1012); -- -------------------- WAIT FOR 100 ns; -- Time=1112 ns CHECK_rst1('1',1112); CHECK_wen1('0',1112); CHECK_ren1('1',1112); -- -------------------- WAIT FOR 100 ns; -- Time=1212 ns CHECK_rst1('1',1212); CHECK_wen1('0',1212); CHECK_ren1('1',1212); -- -------------------- WAIT FOR 100 ns; -- Time=1312 ns CHECK_rst1('1',1312); CHECK_wen1('0',1312); CHECK_ren1('1',1312); -- -------------------- WAIT FOR 100 ns; -- Time=1412 ns CHECK_rst1('1',1412); CHECK_wen1('0',1412); CHECK_ren1('1',1412); -- -------------------- WAIT FOR 100 ns; -- Time=1512 ns CHECK_rst1('1',1512); CHECK_wen1('0',1512); CHECK_ren1('1',1512); -- -------------------- WAIT FOR 100 ns; -- Time=1612 ns CHECK_rst1('1',1612); CHECK_wen1('0',1612); CHECK_ren1('1',1612); -- -------------------- WAIT FOR 100 ns; -- Time=1712 ns CHECK_rst1('1',1712); CHECK_wen1('0',1712); CHECK_ren1('1',1712); -- -------------------- WAIT FOR 100 ns; -- Time=1812 ns CHECK_rst1('1',1812); CHECK_wen1('0',1812); CHECK_ren1('1',1812); -- -------------------- WAIT FOR 100 ns; -- Time=1912 ns CHECK_rst1('1',1912); CHECK_wen1('0',1912); CHECK_ren1('1',1912); -- -------------------- WAIT FOR 100 ns; -- Time=2012 ns CHECK_rst1('1',2012); CHECK_wen1('0',2012); CHECK_ren1('1',2012); -- -------------------- WAIT FOR 100 ns; -- Time=2112 ns CHECK_rst1('1',2112); CHECK_wen1('0',2112); CHECK_ren1('1',2112); -- -------------------- WAIT FOR 100 ns; -- Time=2212 ns CHECK_rst1('1',2212); CHECK_wen1('0',2212); CHECK_ren1('1',2212); -- -------------------- WAIT FOR 100 ns; -- Time=2312 ns CHECK_rst1('1',2312); CHECK_wen1('0',2312); CHECK_ren1('1',2312); -- -------------------- WAIT FOR 100 ns; -- Time=2412 ns CHECK_rst1('1',2412); CHECK_wen1('0',2412); CHECK_ren1('1',2412); -- -------------------- WAIT FOR 100 ns; -- Time=2512 ns CHECK_rst1('1',2512); CHECK_wen1('0',2512); CHECK_ren1('1',2512); -- -------------------- WAIT FOR 100 ns; -- Time=2612 ns CHECK_rst1('1',2612); CHECK_wen1('0',2612); CHECK_ren1('1',2612); -- -------------------- WAIT FOR 100 ns; -- Time=2712 ns CHECK_rst1('1',2712); CHECK_wen1('0',2712); CHECK_ren1('1',2712); -- -------------------- WAIT FOR 100 ns; -- Time=2812 ns CHECK_rst1('1',2812); CHECK_wen1('0',2812); CHECK_ren1('1',2812); -- -------------------- WAIT FOR 100 ns; -- Time=2912 ns CHECK_rst1('1',2912); CHECK_wen1('0',2912); CHECK_ren1('1',2912); -- -------------------- WAIT FOR 100 ns; -- Time=3012 ns CHECK_rst1('1',3012); CHECK_wen1('0',3012); CHECK_ren1('1',3012); -- -------------------- WAIT FOR 100 ns; -- Time=3112 ns CHECK_rst1('1',3112); CHECK_wen1('0',3112); CHECK_ren1('1',3112); -- -------------------- WAIT FOR 100 ns; -- Time=3212 ns CHECK_rst1('1',3212); CHECK_wen1('0',3212); CHECK_ren1('1',3212); -- -------------------- WAIT FOR 100 ns; -- Time=3312 ns CHECK_rst1('1',3312); CHECK_wen1('0',3312); CHECK_ren1('1',3312); -- -------------------- WAIT FOR 100 ns; -- Time=3412 ns CHECK_rst1('1',3412); CHECK_wen1('0',3412); CHECK_ren1('1',3412); -- -------------------- WAIT FOR 100 ns; -- Time=3512 ns CHECK_rst1('1',3512); CHECK_wen1('0',3512); CHECK_ren1('1',3512); -- -------------------- WAIT FOR 100 ns; -- Time=3612 ns CHECK_rst1('1',3612); CHECK_wen1('0',3612); CHECK_ren1('0',3612); -- -------------------- WAIT FOR 100 ns; -- Time=3712 ns CHECK_rst1('1',3712); CHECK_wen1('0',3712); CHECK_ren1('0',3712); -- -------------------- WAIT FOR 100 ns; -- Time=3812 ns CHECK_rst1('1',3812); CHECK_wen1('0',3812); CHECK_ren1('0',3812); -- -------------------- WAIT FOR 100 ns; -- Time=3912 ns CHECK_rst1('1',3912); CHECK_wen1('0',3912); CHECK_ren1('0',3912); -- -------------------- WAIT FOR 100 ns; -- Time=4012 ns CHECK_rst1('1',4012); CHECK_wen1('0',4012); CHECK_ren1('0',4012); -- -------------------- WAIT FOR 100 ns; -- Time=4112 ns CHECK_rst1('1',4112); CHECK_wen1('0',4112); CHECK_ren1('0',4112); -- -------------------- WAIT FOR 100 ns; -- Time=4212 ns CHECK_rst1('1',4212); CHECK_wen1('0',4212); CHECK_ren1('0',4212); -- -------------------- WAIT FOR 100 ns; -- Time=4312 ns CHECK_rst1('1',4312); CHECK_wen1('0',4312); CHECK_ren1('0',4312); -- -------------------- WAIT FOR 100 ns; -- Time=4412 ns CHECK_rst1('1',4412); CHECK_wen1('0',4412); CHECK_ren1('0',4412); -- -------------------- WAIT FOR 100 ns; -- Time=4512 ns CHECK_rst1('1',4512); CHECK_wen1('0',4512); CHECK_ren1('0',4512); -- -------------------- WAIT FOR 100 ns; -- Time=4612 ns CHECK_rst1('1',4612); CHECK_wen1('0',4612); CHECK_ren1('0',4612); -- -------------------- WAIT FOR 100 ns; -- Time=4712 ns CHECK_rst1('1',4712); CHECK_wen1('0',4712); CHECK_ren1('0',4712); -- -------------------- WAIT FOR 100 ns; -- Time=4812 ns CHECK_rst1('1',4812); CHECK_wen1('0',4812); CHECK_ren1('0',4812); -- -------------------- WAIT FOR 88 ns; -- Time=4900 ns acqen <= transport '1'; -- -------------------- WAIT FOR 12 ns; -- Time=4912 ns CHECK_rst1('0',4912); CHECK_wen1('1',4912); CHECK_ren1('1',4912); -- -------------------- WAIT FOR 100 ns; -- Time=5012 ns CHECK_rst1('0',5012); CHECK_wen1('1',5012); CHECK_ren1('1',5012); -- -------------------- WAIT FOR 100 ns; -- Time=5112 ns CHECK_rst1('0',5112); CHECK_wen1('1',5112); CHECK_ren1('1',5112); -- -------------------- WAIT FOR 100 ns; -- Time=5212 ns CHECK_rst1('0',5212); CHECK_wen1('1',5212); CHECK_ren1('1',5212); -- -------------------- WAIT FOR 100 ns; -- Time=5312 ns CHECK_rst1('0',5312); CHECK_wen1('1',5312); CHECK_ren1('1',5312); -- -------------------- WAIT FOR 100 ns; -- Time=5412 ns CHECK_rst1('0',5412); CHECK_wen1('1',5412); CHECK_ren1('1',5412); -- -------------------- WAIT FOR 100 ns; -- Time=5512 ns CHECK_rst1('0',5512); CHECK_wen1('1',5512); CHECK_ren1('1',5512); -- -------------------- WAIT FOR 100 ns; -- Time=5612 ns CHECK_rst1('0',5612); CHECK_wen1('1',5612); CHECK_ren1('1',5612); -- -------------------- WAIT FOR 100 ns; -- Time=5712 ns CHECK_rst1('0',5712); CHECK_wen1('1',5712); CHECK_ren1('1',5712); -- -------------------- WAIT FOR 100 ns; -- Time=5812 ns CHECK_rst1('0',5812); CHECK_wen1('1',5812); CHECK_ren1('1',5812); -- -------------------- WAIT FOR 88 ns; -- Time=5900 ns acqen <= transport '0'; -- -------------------- WAIT FOR 12 ns; -- Time=5912 ns CHECK_rst1('1',5912); CHECK_wen1('0',5912); CHECK_ren1('1',5912); -- -------------------- WAIT FOR 100 ns; -- Time=6012 ns CHECK_rst1('1',6012); CHECK_wen1('0',6012); CHECK_ren1('1',6012); -- -------------------- WAIT FOR 100 ns; -- Time=6112 ns CHECK_rst1('1',6112); CHECK_wen1('0',6112); CHECK_ren1('1',6112); -- -------------------- WAIT FOR 100 ns; -- Time=6212 ns CHECK_rst1('1',6212); CHECK_wen1('0',6212); CHECK_ren1('1',6212); -- -------------------- WAIT FOR 100 ns; -- Time=6312 ns CHECK_rst1('1',6312); CHECK_wen1('0',6312); CHECK_ren1('1',6312); -- -------------------- WAIT FOR 100 ns; -- Time=6412 ns CHECK_rst1('1',6412); CHECK_wen1('0',6412); CHECK_ren1('1',6412); -- -------------------- WAIT FOR 100 ns; -- Time=6512 ns CHECK_rst1('1',6512); CHECK_wen1('0',6512); CHECK_ren1('1',6512); -- -------------------- WAIT FOR 100 ns; -- Time=6612 ns CHECK_rst1('1',6612); CHECK_wen1('0',6612); CHECK_ren1('1',6612); -- -------------------- WAIT FOR 100 ns; -- Time=6712 ns CHECK_rst1('1',6712); CHECK_wen1('0',6712); CHECK_ren1('1',6712); -- -------------------- WAIT FOR 100 ns; -- Time=6812 ns CHECK_rst1('1',6812); CHECK_wen1('0',6812); CHECK_ren1('1',6812); -- -------------------- WAIT FOR 100 ns; -- Time=6912 ns CHECK_rst1('1',6912); CHECK_wen1('0',6912); CHECK_ren1('1',6912); -- -------------------- WAIT FOR 100 ns; -- Time=7012 ns CHECK_rst1('1',7012); CHECK_wen1('0',7012); CHECK_ren1('1',7012); -- -------------------- WAIT FOR 100 ns; -- Time=7112 ns CHECK_rst1('1',7112); CHECK_wen1('0',7112); CHECK_ren1('1',7112); -- -------------------- WAIT FOR 100 ns; -- Time=7212 ns CHECK_rst1('1',7212); CHECK_wen1('0',7212); CHECK_ren1('1',7212); -- -------------------- WAIT FOR 100 ns; -- Time=7312 ns CHECK_rst1('1',7312); CHECK_wen1('0',7312); CHECK_ren1('1',7312); -- -------------------- WAIT FOR 100 ns; -- Time=7412 ns CHECK_rst1('1',7412); CHECK_wen1('0',7412); CHECK_ren1('1',7412); -- -------------------- WAIT FOR 100 ns; -- Time=7512 ns CHECK_rst1('1',7512); CHECK_wen1('0',7512); CHECK_ren1('1',7512); -- -------------------- WAIT FOR 100 ns; -- Time=7612 ns CHECK_rst1('1',7612); CHECK_wen1('0',7612); CHECK_ren1('1',7612); -- -------------------- WAIT FOR 100 ns; -- Time=7712 ns CHECK_rst1('1',7712); CHECK_wen1('0',7712); CHECK_ren1('1',7712); -- -------------------- WAIT FOR 100 ns; -- Time=7812 ns CHECK_rst1('1',7812); CHECK_wen1('0',7812); CHECK_ren1('1',7812); -- -------------------- WAIT FOR 100 ns; -- Time=7912 ns CHECK_rst1('1',7912); CHECK_wen1('0',7912); CHECK_ren1('1',7912); -- -------------------- WAIT FOR 100 ns; -- Time=8012 ns CHECK_rst1('1',8012); CHECK_wen1('0',8012); CHECK_ren1('1',8012); -- -------------------- WAIT FOR 100 ns; -- Time=8112 ns CHECK_rst1('1',8112); CHECK_wen1('0',8112); CHECK_ren1('1',8112); -- -------------------- WAIT FOR 100 ns; -- Time=8212 ns CHECK_rst1('1',8212); CHECK_wen1('0',8212); CHECK_ren1('1',8212); -- -------------------- WAIT FOR 100 ns; -- Time=8312 ns CHECK_rst1('1',8312); CHECK_wen1('0',8312); CHECK_ren1('1',8312); -- -------------------- WAIT FOR 100 ns; -- Time=8412 ns CHECK_rst1('1',8412); CHECK_wen1('0',8412); CHECK_ren1('1',8412); -- -------------------- WAIT FOR 100 ns; -- Time=8512 ns CHECK_rst1('1',8512); CHECK_wen1('0',8512); CHECK_ren1('1',8512); -- -------------------- WAIT FOR 100 ns; -- Time=8612 ns CHECK_rst1('1',8612); CHECK_wen1('0',8612); CHECK_ren1('1',8612); -- -------------------- WAIT FOR 100 ns; -- Time=8712 ns CHECK_rst1('1',8712); CHECK_wen1('0',8712); CHECK_ren1('1',8712); -- -------------------- WAIT FOR 100 ns; -- Time=8812 ns CHECK_rst1('1',8812); CHECK_wen1('0',8812); CHECK_ren1('1',8812); -- -------------------- WAIT FOR 100 ns; -- Time=8912 ns CHECK_rst1('1',8912); CHECK_wen1('0',8912); CHECK_ren1('1',8912); -- -------------------- WAIT FOR 100 ns; -- Time=9012 ns CHECK_rst1('1',9012); CHECK_wen1('0',9012); CHECK_ren1('1',9012); -- -------------------- WAIT FOR 100 ns; -- Time=9112 ns CHECK_rst1('1',9112); CHECK_wen1('0',9112); CHECK_ren1('0',9112); -- -------------------- WAIT FOR 100 ns; -- Time=9212 ns CHECK_rst1('1',9212); CHECK_wen1('0',9212); CHECK_ren1('0',9212); -- -------------------- WAIT FOR 100 ns; -- Time=9312 ns CHECK_rst1('1',9312); CHECK_wen1('0',9312); CHECK_ren1('0',9312); -- -------------------- WAIT FOR 100 ns; -- Time=9412 ns CHECK_rst1('1',9412); CHECK_wen1('0',9412); CHECK_ren1('0',9412); -- -------------------- WAIT FOR 100 ns; -- Time=9512 ns CHECK_rst1('1',9512); CHECK_wen1('0',9512); CHECK_ren1('0',9512); -- -------------------- WAIT FOR 100 ns; -- Time=9612 ns CHECK_rst1('1',9612); CHECK_wen1('0',9612); CHECK_ren1('0',9612); -- -------------------- WAIT FOR 100 ns; -- Time=9712 ns CHECK_rst1('1',9712); CHECK_wen1('0',9712); CHECK_ren1('0',9712); -- -------------------- WAIT FOR 100 ns; -- Time=9812 ns CHECK_rst1('1',9812); CHECK_wen1('0',9812); CHECK_ren1('0',9812); -- -------------------- WAIT FOR 100 ns; -- Time=9912 ns CHECK_rst1('1',9912); CHECK_wen1('0',9912); CHECK_ren1('0',9912); -- -------------------- WAIT FOR 100 ns; -- Time=10012 ns -- -------------------- IF (TX_ERROR = 0) THEN STD.TEXTIO.write(TX_OUT,string'("No errors or warnings")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; ELSE STD.TEXTIO.write(TX_OUT, TX_ERROR); STD.TEXTIO.write(TX_OUT, string'( " errors found in simulation")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Errors found during simulation" SEVERITY FAILURE; END IF; END PROCESS; END testbench_arch; CONFIGURATION fifo1_cfg OF fifo1_tbw IS FOR testbench_arch END FOR; END fifo1_cfg;