-- C:\JFB\XILINX\MWD\WORK\CHANNELCTRL\CHNCTRL
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Tue Dec 07 09:43:16 2004

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY fifo1_tbw IS
END fifo1_tbw;

ARCHITECTURE testbench_arch OF fifo1_tbw IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "c:\jfb\xilinx\mwd\work\channelctrl\chnctrl\fifo1_tbw.ano";
	COMPONENT fifo1
		PORT (
			reset : In  std_logic;
			clk : In  std_logic;
			acqen : In  std_logic;
			rst1 : Out  std_logic;
			wen1 : Out  std_logic;
			ren1 : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL acqen : std_logic;
	SIGNAL rst1 : std_logic;
	SIGNAL wen1 : std_logic;
	SIGNAL ren1 : std_logic;

BEGIN
	UUT : fifo1
	PORT MAP (
		reset => reset,
		clk => clk,
		acqen => acqen,
		rst1 => rst1,
		wen1 => wen1,
		ren1 => ren1
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_rst1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",rst1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, rst1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_wen1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",wen1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, wen1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_ren1(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",ren1,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, ren1);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		clk <= transport '1';
		WAIT FOR 6 ns;
		TX_TIME := TX_TIME + 6;
		ANNOTATE_rst1(TX_TIME);
		ANNOTATE_wen1(TX_TIME);
		ANNOTATE_ren1(TX_TIME);
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		clk <= transport '0';
		WAIT FOR 44 ns;
		TX_TIME := TX_TIME + 44;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		reset <= transport '0';
		acqen <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		reset <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		acqen <= transport '0';
		-- --------------------
		WAIT FOR 4500 ns; -- Time=4900 ns
		acqen <= transport '1';
		-- --------------------
		WAIT FOR 1000 ns; -- Time=5900 ns
		acqen <= transport '0';
		-- --------------------
		WAIT FOR 4112 ns; -- Time=10012 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION fifo1_cfg OF fifo1_tbw IS
	FOR testbench_arch
	END FOR;
END fifo1_cfg;