-- VHDL Instantiation Created from source file fifo1.vhd -- 08:17:20 02/27/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT fifo1
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		acqen : IN std_logic;          
		rst1 : OUT std_logic;
		wen1 : OUT std_logic;
		ren1 : OUT std_logic
		);
	END COMPONENT;

	Inst_fifo1: fifo1 PORT MAP(
		reset => ,
		clk => ,
		acqen => ,
		rst1 => ,
		wen1 => ,
		ren1 => 
	);