Release 6.1.03i - xst G.26 Copyright (c) 1995-2003 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.19 s | Elapsed : 0.00 / 0.00 s --> Reading design: fifo1.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 6) Low Level Synthesis 7) Final Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : fifo1.prj Input Format : mixed Ignore Synthesis Constraint File : NO Verilog Include Directory : ---- Target Parameters Output File Name : fifo1 Output Format : NGC Target Device : xc9500xl ---- Source Options Top Module Name : fifo1 Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Mux Extraction : YES Resource Sharing : YES ---- Target Options Add IO Buffers : YES Equivalent register Removal : YES MACRO Preserve : YES XOR Preserve : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : YES RTL Output : Yes Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain ---- Other Options lso : fifo1.lso verilog2001 : YES Clock Enable : YES wysiwyg : NO ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd in Library work. Architecture behavioral of Entity fifo1 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set property "ENUM_ENCODING = 00 01 10" for signal . Set property "ENUM_ENCODING = 00 01 10" for signal . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is C:/jfb/Xilinx/MWD/Work/ChannelCtrl/Chnctrl/fifo1.vhd. Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 7 | | Inputs | 2 | | Outputs | 4 | | Reset type | asynchronous | | Encoding | automatic | | State register | d flip-flops | ----------------------------------------------------------------------- Found 5-bit comparator less for signal <$n0012> created at line 144. Found 5-bit adder for signal <$n0014> created at line 145. Found 5-bit register for signal . Found 1-bit register for signal . Summary: inferred 1 Finite State Machine(s). inferred 1 D-type flip-flop(s). inferred 1 Adder/Subtracter(s). inferred 1 Comparator(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Registers : 2 5-bit register : 1 1-bit register : 1 # Adders/Subtractors : 1 5-bit adder : 1 # Comparators : 1 5-bit comparator less : 1 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Selecting encoding for FSM_0 ... Encoding for FSM_0 is Gray flip-flop = D ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... implementation constraint: INIT=s : cnt_1 implementation constraint: INIT=s : cnt_2 implementation constraint: INIT=s : cnt_0 implementation constraint: INIT=s : cnt_4 implementation constraint: INIT=s : cnt_3 ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : fifo1.ngr Top Level Output File Name : fifo1 Output Format : NGC Optimization Goal : Speed Keep Hierarchy : YES Target Technology : xc9500xl Macro Preserve : YES XOR Preserve : YES Clock Enable : YES wysiwyg : NO Design Statistics # IOs : 6 Macro Statistics : # Registers : 6 # 1-bit register : 6 # Comparators : 1 # 5-bit comparator less : 1 # Xors : 4 # 1-bit xor2 : 4 Cell Usage : # BELS : 42 # AND2 : 19 # AND3 : 1 # AND4 : 1 # INV : 17 # XOR2 : 4 # FlipFlops/Latches : 8 # FDC : 2 # FDCE : 5 # FDP : 1 # IO Buffers : 6 # IBUF : 3 # OBUF : 3 ========================================================================= CPU : 0.78 / 1.06 s | Elapsed : 1.00 / 1.00 s --> Total memory usage is 45564 kilobytes