cpldfit: version G.26 Xilinx Inc. Fitter Report Design Name: fifo1 Date: 3- 2-2004, 6:09PM Device Used: XC95144XL-5-TQ100 Fitting Status: Successful **************************** Resource Summary **************************** Macrocells Product Terms Registers Pins Function Block Used Used Used Used Inputs Used 10 /144 ( 7%) 30 /720 ( 4%) 9 /144 ( 6%) 6 /81 ( 7%) 14 /432 ( 3%) PIN RESOURCES: Signal Type Required Mapped | Pin Type Used Remaining ------------------------------------|--------------------------------------- Input : 1 1 | I/O : 4 69 Output : 3 3 | GCK/IO : 1 2 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 1 1 | GSR/IO : 1 0 GTS : 0 0 | GSR : 1 1 | ---- ---- Total 6 6 MACROCELL RESOURCES: Total Macrocells Available 144 Registered Macrocells 9 Non-registered Macrocell driving I/O 1 GLOBAL RESOURCES: Signal 'clk' mapped onto global clock net GCK1. Global output enable net(s) unused. Signal 'reset' mapped onto global set/reset net GSR. POWER DATA: There are 10 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). There are a total of 10 macrocells used (MC). End of Resource Summary *************** Summary of Required Resources ****************** ** LOGIC ** Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init Name Pt Used Mode Rate # Type Use State cnt<0> 4 7 FB1_16 STD (b) (b) SET cnt<1> 4 7 FB1_15 STD 20 I/O (b) SET cnt<2> 5 7 FB1_18 STD (b) (b) SET cnt<3> 5 7 FB1_17 STD 22 GCK/I/O GCK SET cnt<4> 3 7 FB1_14 STD 19 I/O (b) SET delay 2 6 FB1_13 STD (b) (b) RESET ren1 1 2 FB1_2 STD FAST 11 I/O O rst1 2 3 FB3_5 STD FAST 24 I/O O RESET state_FFD2 2 4 FB3_18 STD (b) (b) RESET wen1 2 3 FB4_2 STD FAST 87 I/O O SET ** INPUTS ** Signal Loc Pin Pin Pin Name # Type Use acqen FB2_14 8 I/O I clk FB1_17 22 GCK/I/O GCK reset FB2_2 99 GSR/I/O GSR End of Resources *********************Function Block Resource Summary*********************** Function # of FB Inputs Signals Total O/IO IO Block Macrocells Used Used Pt Used Req Avail FB1 7 7 7 24 1/0 11 FB2 0 0 0 0 0/0 10 FB3 2 4 4 4 1/0 10 FB4 1 3 3 2 1/0 10 FB5 0 0 0 0 0/0 10 FB6 0 0 0 0 0/0 10 FB7 0 0 0 0 0/0 10 FB8 0 0 0 0 0/0 10 ---- ----- ----- ----- 10 30 3/0 81 *********************************** FB1 *********************************** Number of function block inputs used/remaining: 7/47 Number of signals used by logic mapping into function block: 7 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB1_1 (b) ren1 1 0 0 4 FB1_2 STD 11 I/O O (unused) 0 0 0 5 FB1_3 12 I/O (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 13 I/O (unused) 0 0 0 5 FB1_6 14 I/O (unused) 0 0 0 5 FB1_7 (b) (unused) 0 0 0 5 FB1_8 15 I/O (unused) 0 0 0 5 FB1_9 16 I/O (unused) 0 0 0 5 FB1_10 (b) (unused) 0 0 0 5 FB1_11 17 I/O (unused) 0 0 0 5 FB1_12 18 I/O delay 2 0 0 3 FB1_13 STD (b) (b) cnt<4> 3 0 0 2 FB1_14 STD 19 I/O (b) cnt<1> 4 0 0 1 FB1_15 STD 20 I/O (b) cnt<0> 4 0 0 1 FB1_16 STD (b) (b) cnt<3> 5 0 0 0 FB1_17 STD 22 GCK/I/O GCK cnt<2> 5 0 0 0 FB1_18 STD (b) (b) Signals Used by Logic in Function Block 1: cnt<0> 4: cnt<3> 6: rst1 2: cnt<1> 5: cnt<4> 7: state_FFD2 3: cnt<2> Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs ren1 .....XX................................. 2 2 delay .XXXXXX................................. 6 6 cnt<4> XXXXXXX................................. 7 7 cnt<1> XXXXXXX................................. 7 7 cnt<0> XXXXXXX................................. 7 7 cnt<3> XXXXXXX................................. 7 7 cnt<2> XXXXXXX................................. 7 7 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB2 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB2_1 (b) (unused) 0 0 0 5 FB2_2 99 GSR/I/O GSR (unused) 0 0 0 5 FB2_3 (b) (unused) 0 0 0 5 FB2_4 (b) (unused) 0 0 0 5 FB2_5 1 GTS/I/O (unused) 0 0 0 5 FB2_6 2 GTS/I/O (unused) 0 0 0 5 FB2_7 (b) (unused) 0 0 0 5 FB2_8 3 GTS/I/O (unused) 0 0 0 5 FB2_9 4 GTS/I/O (unused) 0 0 0 5 FB2_10 (b) (unused) 0 0 0 5 FB2_11 6 I/O (unused) 0 0 0 5 FB2_12 7 I/O (unused) 0 0 0 5 FB2_13 (b) (unused) 0 0 0 5 FB2_14 8 I/O I (unused) 0 0 0 5 FB2_15 9 I/O (unused) 0 0 0 5 FB2_16 (b) (unused) 0 0 0 5 FB2_17 10 I/O (unused) 0 0 0 5 FB2_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB3 *********************************** Number of function block inputs used/remaining: 4/50 Number of signals used by logic mapping into function block: 4 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 23 GCK/I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) rst1 2 0 0 3 FB3_5 STD 24 I/O O (unused) 0 0 0 5 FB3_6 25 I/O (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 27 GCK/I/O (unused) 0 0 0 5 FB3_9 28 I/O (unused) 0 0 0 5 FB3_10 (b) (unused) 0 0 0 5 FB3_11 29 I/O (unused) 0 0 0 5 FB3_12 30 I/O (unused) 0 0 0 5 FB3_13 (b) (unused) 0 0 0 5 FB3_14 32 I/O (unused) 0 0 0 5 FB3_15 33 I/O (unused) 0 0 0 5 FB3_16 (b) (unused) 0 0 0 5 FB3_17 34 I/O state_FFD2 2 0 0 3 FB3_18 STD (b) (b) Signals Used by Logic in Function Block 1: acqen 3: rst1 4: state_FFD2 2: delay Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs rst1 X.XX.................................... 3 3 state_FFD2 XXXX.................................... 4 4 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB4 *********************************** Number of function block inputs used/remaining: 3/51 Number of signals used by logic mapping into function block: 3 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB4_1 (b) wen1 2 0 0 3 FB4_2 STD 87 I/O O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 89 I/O (unused) 0 0 0 5 FB4_6 90 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 91 I/O (unused) 0 0 0 5 FB4_9 92 I/O (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 93 I/O (unused) 0 0 0 5 FB4_12 94 I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 95 I/O (unused) 0 0 0 5 FB4_15 96 I/O (unused) 0 0 0 5 FB4_16 (b) (unused) 0 0 0 5 FB4_17 97 I/O (unused) 0 0 0 5 FB4_18 (b) Signals Used by Logic in Function Block 1: acqen 2: rst1 3: state_FFD2 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs wen1 XXX..................................... 3 3 0----+----1----+----2----+----3----+----4 0 0 0 0 Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB5 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 35 I/O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 36 I/O (unused) 0 0 0 5 FB5_6 37 I/O (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 39 I/O (unused) 0 0 0 5 FB5_9 40 I/O (unused) 0 0 0 5 FB5_10 (b) (unused) 0 0 0 5 FB5_11 41 I/O (unused) 0 0 0 5 FB5_12 42 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 43 I/O (unused) 0 0 0 5 FB5_15 46 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 49 I/O (unused) 0 0 0 5 FB5_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB6 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 74 I/O (unused) 0 0 0 5 FB6_3 (b) (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 76 I/O (unused) 0 0 0 5 FB6_6 77 I/O (unused) 0 0 0 5 FB6_7 (b) (unused) 0 0 0 5 FB6_8 78 I/O (unused) 0 0 0 5 FB6_9 79 I/O (unused) 0 0 0 5 FB6_10 (b) (unused) 0 0 0 5 FB6_11 80 I/O (unused) 0 0 0 5 FB6_12 81 I/O (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 82 I/O (unused) 0 0 0 5 FB6_15 85 I/O (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 86 I/O (unused) 0 0 0 5 FB6_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB7 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 50 I/O (unused) 0 0 0 5 FB7_3 (b) (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 52 I/O (unused) 0 0 0 5 FB7_6 53 I/O (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 54 I/O (unused) 0 0 0 5 FB7_9 55 I/O (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 56 I/O (unused) 0 0 0 5 FB7_12 58 I/O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 59 I/O (unused) 0 0 0 5 FB7_15 60 I/O (unused) 0 0 0 5 FB7_16 (b) (unused) 0 0 0 5 FB7_17 61 I/O (unused) 0 0 0 5 FB7_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. *********************************** FB8 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin Name Pt Pt Pt Pt Mode # Type Use (unused) 0 0 0 5 FB8_1 (b) (unused) 0 0 0 5 FB8_2 63 I/O (unused) 0 0 0 5 FB8_3 (b) (unused) 0 0 0 5 FB8_4 (b) (unused) 0 0 0 5 FB8_5 64 I/O (unused) 0 0 0 5 FB8_6 65 I/O (unused) 0 0 0 5 FB8_7 (b) (unused) 0 0 0 5 FB8_8 66 I/O (unused) 0 0 0 5 FB8_9 67 I/O (unused) 0 0 0 5 FB8_10 (b) (unused) 0 0 0 5 FB8_11 68 I/O (unused) 0 0 0 5 FB8_12 70 I/O (unused) 0 0 0 5 FB8_13 (b) (unused) 0 0 0 5 FB8_14 71 I/O (unused) 0 0 0 5 FB8_15 72 I/O (unused) 0 0 0 5 FB8_16 (b) (unused) 0 0 0 5 FB8_17 73 I/O (unused) 0 0 0 5 FB8_18 (b) Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pwr Mode - Macrocell power mode Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. ;;-----------------------------------------------------------------;; ; Implemented Equations. !cnt<0>.T = !cnt<0> & !rst1 # !cnt<0> & state_FFD2 # cnt<1> & cnt<2> & cnt<3> & cnt<4> & rst1 & !state_FFD2; cnt<0>.CLK = clk; // GCK cnt<0>.AR = !rst1; cnt<1>.D = cnt<0> & !cnt<1> & rst1 & !state_FFD2 # !cnt<0> & cnt<1> & rst1 & !state_FFD2 # cnt<1> & cnt<2> & cnt<3> & cnt<4> & rst1 & !state_FFD2; cnt<1>.CLK = clk; // GCK cnt<1>.AR = !rst1; cnt<2>.D = !cnt<0> & cnt<2> & rst1 & !state_FFD2 # !cnt<1> & cnt<2> & rst1 & !state_FFD2 # cnt<0> & cnt<1> & !cnt<2> & rst1 & !state_FFD2 # cnt<2> & cnt<3> & cnt<4> & rst1 & !state_FFD2; cnt<2>.CLK = clk; // GCK cnt<2>.AR = !rst1; cnt<3>.T = cnt<3> & !rst1 # cnt<3> & state_FFD2 # cnt<0> & cnt<1> & cnt<2> & cnt<3> & !cnt<4> # cnt<0> & cnt<1> & cnt<2> & !cnt<3> & rst1 & !state_FFD2; cnt<3>.CLK = clk; // GCK cnt<3>.AR = !rst1; cnt<4>.D = cnt<4> & rst1 & !state_FFD2 # cnt<0> & cnt<1> & cnt<2> & cnt<3> & rst1 & !state_FFD2; cnt<4>.CLK = clk; // GCK cnt<4>.AR = !rst1; !delay.D = cnt<1> & cnt<2> & cnt<3> & cnt<4> & rst1 & !state_FFD2; delay.CLK = clk; // GCK delay.AP = !rst1; !ren1 = rst1 & state_FFD2; rst1.D = !acqen & rst1 # !acqen & !state_FFD2; rst1.CLK = clk; // GCK !rst1.AR = reset; // GSR state_FFD2.D = !acqen & rst1 & state_FFD2 # !acqen & rst1 & !delay; state_FFD2.CLK = clk; // GCK !state_FFD2.AR = reset; // GSR !wen1.D = !acqen & rst1 # !acqen & !state_FFD2; wen1.CLK = clk; // GCK !wen1.AP = reset; // GSR Legend: .COMB = combinational node mapped to the same physical macrocell as the FastInput "signal" (not logically related) **************************** Device Pin Out **************************** Device : XC95144XL-5-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-5-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 TIE 51 VCC 2 TIE 52 TIE 3 TIE 53 TIE 4 TIE 54 TIE 5 VCC 55 TIE 6 TIE 56 TIE 7 TIE 57 VCC 8 acqen 58 TIE 9 TIE 59 TIE 10 TIE 60 TIE 11 ren1 61 TIE 12 TIE 62 GND 13 TIE 63 TIE 14 TIE 64 TIE 15 TIE 65 TIE 16 TIE 66 TIE 17 TIE 67 TIE 18 TIE 68 TIE 19 TIE 69 GND 20 TIE 70 TIE 21 GND 71 TIE 22 clk 72 TIE 23 TIE 73 TIE 24 rst1 74 TIE 25 TIE 75 GND 26 VCC 76 TIE 27 TIE 77 TIE 28 TIE 78 TIE 29 TIE 79 TIE 30 TIE 80 TIE 31 GND 81 TIE 32 TIE 82 TIE 33 TIE 83 TDO 34 TIE 84 GND 35 TIE 85 TIE 36 TIE 86 TIE 37 TIE 87 wen1 38 VCC 88 VCC 39 TIE 89 TIE 40 TIE 90 TIE 41 TIE 91 TIE 42 TIE 92 TIE 43 TIE 93 TIE 44 GND 94 TIE 45 TDI 95 TIE 46 TIE 96 TIE 47 TMS 97 TIE 48 TCK 98 VCC 49 TIE 99 reset 50 TIE 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PE = Port Enable pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-5-TQ100 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Set Unused I/O Pin Termination : FLOAT Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 50