MODELDATA
MODELDATA_VERSION "v1998.8"
DESIGN "fifo1";

/* port drive, load, max capacitance and max transition in data file */
PORTDATA
clk: MAXTRANS(0.0);
acqen: MAXTRANS(0.0);
reset: MAXTRANS(0.0);
rst1: MAXTRANS(0.0);
ren1: MAXTRANS(0.0);
wen1: MAXTRANS(0.0);
ENDPORTDATA

/* timing arc data */
TIMINGDATA

ARCDATA
clk_rst1_delay:
CELL_RISE(scalar) {
  VALUES("3.5");
}
CELL_FALL(scalar) {
  VALUES("3.5");
}
ENDARCDATA

ARCDATA
clk_ren1_delay:
CELL_RISE(scalar) {
  VALUES("6.9");
}
CELL_FALL(scalar) {
  VALUES("6.9");
}
ENDARCDATA

ARCDATA
clk_wen1_delay:
CELL_RISE(scalar) {
  VALUES("3.5");
}
CELL_FALL(scalar) {
  VALUES("3.5");
}
ENDARCDATA

ARCDATA
acqen_clk_setup:
CONSTRAINT(scalar) {
  VALUES("6");
}
ENDARCDATA

ARCDATA
acqen_clk_hold:
CONSTRAINT(scalar) {
  VALUES("-2.3");
}
ENDARCDATA

ENDTIMINGDATA
ENDMODELDATA