-- VHDL Instantiation Created from source file dffen.vhd -- 12:50:20 02/03/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT dffen
	PORT(
		reset_n : IN std_logic;
		clk : IN std_logic;
		en_n : IN std_logic;
		din : IN std_logic;          
		qout : OUT std_logic
		);
	END COMPONENT;

	Inst_dffen: dffen PORT MAP(
		reset_n => ,
		clk => ,
		en_n => ,
		din => ,
		qout => 
	);