-- VHDL Instantiation Created from source file decim.vhd -- 14:09:14 02/26/2004
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT decim
	PORT(
		reset : IN std_logic;
		clk : IN std_logic;
		decim_ratio : IN std_logic_vector(1 downto 0);
		decim_en : IN std_logic;
		dflag : IN std_logic;          
		decim_sig : OUT std_logic
		);
	END COMPONENT;

	Inst_decim: decim PORT MAP(
		reset => ,
		clk => ,
		decim_ratio => ,
		decim_en => ,
		dflag => ,
		decim_sig => 
	);